Local Replica Generator Circuit for Joint GNSS Doppler Compensation
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Solution Overview
Problem
GNSS receivers face challenges in dealing with Doppler effects, requiring complex circuit structures to separately handle code Doppler and carrier Doppler, which complicates hardware and software efforts, and frequency-domain correlation accuracy is constrained by FFT size.
Innovation Solution
A local replica generator circuit that includes a code generator and Doppler-shift generator, capable of joint code Doppler and carrier Doppler compensation, up-sampling the local replica to any sampling rate, and outputting all samples per clock cycle for block-wise correlation processing, reducing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuits are used to handle code Doppler and carrier Doppler, then Doppler compensation can be achieved, but device complexity increases
Solution Approach 1:
The patent combines code Doppler compensation and carrier Doppler compensation into a single integrated local replica generator circuit. The control circuit generates control outputs that simultaneously account for both code Doppler shift and carrier Doppler shift, eliminating the need for separate handling circuits and reducing overall device complexity while maintaining compensation accuracy.
Solution Approach 2:
The local replica generator circuit is designed to perform multiple functions: generating code sequences, applying code Doppler compensation, generating carrier Doppler compensation signals, and producing the final local replica output. This multi-functional approach allows a single circuit to replace what would traditionally require multiple separate circuits.
2Measurement precision
If FFT size is increased to improve frequency-domain correlation accuracy, then measurement precision improves, but device complexity and processing time increase
Solution Approach 1:
The patent applies Doppler compensation before the correlation processing stage. By pre-compensating for both code and carrier Doppler effects in the local replica generation, the correlation process becomes more efficient and accurate without requiring excessively large FFT sizes, thus avoiding the complexity associated with very large transform operations.
3Reliability
If complex circuit structures are used to handle Doppler effects, then Doppler compensation accuracy improves, but ease of operation deteriorates
Solution Approach 1:
The patent merges code Doppler compensation and carrier Doppler compensation into a single integrated circuit operation. The control circuit generates control outputs that simultaneously handle both compensation requirements, simplifying the hardware implementation process and making the system easier to operate while maintaining high compensation accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design achieves accurate Doppler compensation without being constrained by FFT size, simplifying the circuit structure and enabling efficient block-wise correlation processing.
Implementation Method 1
Doppler shift of the satellite signal is caused by the relative motion of the GNSS receiver and the GNSS satellite. Hence, the GNSS baseband received signal suffers the Doppler effect, including code Doppler and carrier Doppler
Implementation Method 2
Doppler shift of the satellite signal is caused by the relative motion of the GNSS receiver and the GNSS satellite. Hence, the GNSS baseband received signal suffers the Doppler effect, including code Doppler and carrier Doppler
Implementation Method 3
A GNSS satellite signal is modulated by a pseudo random noise (PRN) code
Data Source
AI summary
A code generator circuit includes a control circuit and a code sequence processing circuit. The control circuit updates an accumulated value by accumulating an increment value per clock cycle, and refers to the accumulated value to generate a control output per clock cycle, wherein the increment value is set based on at least one of a Doppler shift, a block size, and a local replica output sampling rate. The code sequence processing circuit generates a code generator output according to the control output of the control circuit.