Local Scope Atomic Instruction for Cache Line Locking
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Solution Overview
Problem
In multi-core processors with shared cache memories, existing atomic instructions for data sharing between cores face inefficiencies due to system-wide locking mechanisms that restrict access and cause significant latency, particularly when using global scope atomic instructions, which can hinder performance by locking entire memory zones and restricting access to other processes.
Innovation Solution
Introducing local scope atomic instructions that operate within intermediate cache levels, such as the L2 cache, allowing atomic operations to be executed without locking the entire system memory, thereby reducing latency and enabling concurrent access to other cache lines and system memory, and utilizing the Memory Management Unit (MMU) to differentiate instruction scopes through virtual address attributes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If system-wide locking mechanisms are used for atomic instructions, then atomicity is guaranteed, but access latency increases significantly and system memory accessibility is restricted
Solution Approach 1:
The invention segments the locking scope from system-wide to cache-line level. Instead of locking the entire system memory for atomic operations, only the specific cache line containing the target variable is locked. This segmentation allows other cores to continue accessing unrelated memory regions without interference, significantly reducing access latency while maintaining atomicity for the targeted operation.
Solution Approach 2:
The invention applies local quality by making the locking mechanism localized to specific cache lines rather than applying a uniform system-wide lock. Each cache line can be independently locked and unlocked, allowing different regions of memory to have different access states simultaneously. This local approach resolves the contradiction by providing atomicity where needed while preserving system-wide accessibility elsewhere.
2Reliability
If system-wide locking is used for atomic operations, then consistency is maintained, but productivity of concurrent operations decreases
Solution Approach 1:
By segmenting the critical section to only include the specific cache line being modified, the invention enables multiple concurrent atomic operations on different cache lines to proceed simultaneously. This segmentation transforms a serial system-wide locking mechanism into parallelizable fine-grained locks, dramatically improving concurrent operation throughput while preserving consistency through proper cache coherence protocols.
Solution Approach 2:
The invention applies partial locking by acquiring locks only for the specific cache lines involved in atomic operations, rather than locking the entire system memory. This partial action approach provides sufficient consistency for the atomic operation while leaving other memory regions accessible, thereby maintaining high productivity for concurrent operations that do not interfere with each other.
3Loss of time
If cache line locking is implemented, then access latency is reduced, but device complexity increases
Solution Approach 1:
The cache coherence protocol itself is leveraged to provide the locking mechanism, rather than implementing a separate complex locking hardware structure. The existing invalidate and update messages in the cache coherence protocol are repurposed to signal lock acquisition and release, allowing the system to use its existing infrastructure for fine-grained locking without adding significant complexity.
Solution Approach 2:
The cache coherence protocol messages serve multiple functions: maintaining cache consistency across cores and simultaneously providing the locking mechanism for atomic operations. This multi-functionality eliminates the need for dedicated locking hardware or complex interlocking protocols, reducing overall device complexity while achieving fine-grained locking benefits.
Data Source
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AI summary
The invention relates to a method for updating a variable shared between several processor cores. The following steps are implemented during the execution in one of the cores of a local scope atomic read-modify-write (AFA) instruction with the memory address (al) of the shared variable as a parameter: perform the operations of the atomic instruction in a cache line (L(al)) allocated to the memory address; and lock the cache line locally (LCK) while allowing access to the shared variable by cores connected to another cache memory of the same level during the execution of the local scope atomic instruction.