Local Word Line Driver Deep Trench Isolation
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Solution Overview
Problem
In high-density memory devices, the shrinking spacings between high voltage NMOS devices due to chip size limitations lead to worsened drain-source breakdown voltage and hinder Y-pitch shrinkage, as conventional p-type field implants worsen the breakdown voltage and require additional masks and processes.
Innovation Solution
The implementation of deep trench isolation structures between transistor structures in local word line driver devices eliminates the need for p-type field implants, allowing for more controlled dimensions and reduced spacings, thereby improving storage density and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p-type field implant is formed between HVN devices to suppress punch through, then punch through is suppressed, but drain-source breakdown voltage deteriorates and fabrication complexity increases
Solution Approach 1:
The patent extracts and removes the p-type field implant process from the fabrication sequence. Instead of forming p-type field implants between HVN devices, the invention uses alternative structures (such as n-well regions or other isolation techniques) that eliminate the need for this problematic implant step, thereby reducing fabrication complexity while maintaining punch-through suppression
Solution Approach 2:
The patent changes the doping type or isolation mechanism from p-type field implant to alternative structures. By modifying the fundamental approach to field isolation (changing from p-type doping to other methods), the invention resolves the contradiction by achieving punch-through suppression without the adverse effects on breakdown voltage and fabrication complexity
2Reliability
If p+ tap is formed between HVN devices in Y-direction to suppress latch up, then latch up is suppressed, but spacing between HVN devices cannot be reduced and Y-pitch shrinkage is hindered
Solution Approach 1:
The patent removes the requirement for p+ tap structures by using alternative isolation and suppression techniques. By extracting this constraint from the design, the invention allows Y-pitch to be reduced without compromising latch-up suppression, enabling continued scaling in the Y-direction
Solution Approach 2:
The patent addresses the Y-pitch constraint by moving the suppression mechanism to a different dimensional approach or location. Instead of requiring horizontal spacing for p+ taps, the invention uses vertical or alternative spatial arrangements that allow tighter Y-pitch while maintaining reliability
3Quantity of substance
If spacing between HVN devices is reduced to increase storage density, then storage density improves, but drain-source breakdown voltage deteriorates
Solution Approach 1:
The patent introduces intermediary structures or materials between HVN devices that enable closer spacing while maintaining electrical isolation. These intermediary elements act as mediators that allow reduced spacing for higher density without compromising the breakdown voltage, resolving the contradiction between density and reliability
Data Source
AI summary
Local word line driver device, memory device, and fabrication method are provided. A local word line driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are configured in rows and columns. The substrate includes a plurality of first field regions each between adjacent rows of the transistor structures, and a plurality of second field regions each between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one field region of: the plurality of first field regions or the plurality of second field regions, of the substrate.