Local Write Lines for Memory Cell Subsets

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing memory circuits face challenges in efficiently writing data to individual subsets of memory cells within a word of data, leading to issues with data write performance and signal propagation delays.

Innovation Solution

The implementation of local write lines and selection logic allows for selective writing to subsets of memory cells, enabling byte-write enable operations and improving data write performance by mitigating loading and signal propagation issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single global write word line is used to control all memory cells in a word, then the circuit structure is simple, but signal propagation delays increase and data write performance deteriorates

Engineering Contradiction:
Improvecircuit structureVSAvoiddata write performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the memory cell array into multiple subsets along the word line direction, with each subset controlled by a separate local write word line. This segmentation reduces the length of each word line segment, thereby reducing signal propagation delays and improving data write performance while maintaining reasonable circuit complexity through systematic organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local write word lines that are specifically tailored to control individual subsets of memory cells. Each local write word line is optimized for its specific subset, allowing for reduced signal propagation distance and improved write performance in that local region, while the global write word line provides overall coordination.

Inventive Principle:
Principle #3Local quality

2Productivity

If local write word lines are implemented to improve signal propagation, then data write performance improves, but device complexity increases

Engineering Contradiction:
Improvedata write performanceVSAvoidcircuit structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The global write word line serves multiple functions: it provides the primary write enable signal to all subsets and also coordinates the activation of local write word lines. This multi-functionality reduces the need for entirely separate control mechanisms for each subset, thereby limiting the increase in device complexity while achieving improved signal propagation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The global write word line acts as an intermediary that coordinates between the control logic and the local write word lines. It receives write enable signals and distributes them appropriately to activate the necessary local write word lines, thereby managing the complexity of having multiple local control lines while maintaining improved data write performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If the entire word line is activated for writing, then all memory cells can be written simultaneously, but the ability to write partial words is lost

Engineering Contradiction:
Improvewrite throughputVSAvoidpartial write capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

By dividing the memory cell array into multiple subsets each controlled by a local write word line, the patent enables selective activation of individual subsets or combinations of subsets. This segmentation allows partial word writes to specific subsets while maintaining the capability to activate all subsets simultaneously for full word writes, thereby achieving both partial write versatility and full write throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of local write word lines based on write enable signals and subset selection signals. This dynamic activation allows the system to adaptively select which subsets to write to in each operation, enabling flexible partial word writes while maintaining the option to activate all lines for full word writes, thus achieving both versatility and throughput.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250078889A1Systems and Methods for Memory Operation Using Local Word Lines
Publication Date: 2025.03.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250078889A1 patent drawing
  • US20250078889A1 patent drawing
  • US20250078889A1 patent drawing

AI summary

Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.