Local X-Decoder Vertical Stacking for Memory Array Reliability
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Solution Overview
Problem
Conventional local x-decoders in memory arrays face challenges in maintaining electrical fields during erase operations due to transistor degradation, and the addition of extra transistors to mitigate this issue increases circuit area, violating the limited vertical pitch of memory cell arrays.
Innovation Solution
A two-sided memory array design with four local x-decoders on each side, featuring cascode transistors and specific transistor orientations, allows for the implementation of extra transistors without increasing the vertical pitch by rotating transistor orientation and arranging signal lines to prevent shorting, while maintaining a narrow vertical pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extra transistors are added to maintain electrical fields during erase operations, then reliability is improved, but device area increases
Solution Approach 1:
The patent transitions from a conventional planar layout to a vertical three-dimensional stacked architecture. Local x-decoders are stacked vertically above memory cell blocks, with word lines extending vertically through multiple decoder levels. This vertical stacking enables extra transistors to be accommodated in the vertical dimension rather than consuming additional horizontal area, resolving the contradiction between reliability improvement and area increase.
Solution Approach 2:
The patent implements a nested structure where local x-decoders are positioned within and above memory cell blocks. The word lines pass through multiple decoder levels, creating a nested arrangement where decoders are embedded in the vertical space above the memory cells they control. This nesting allows the circuit to maintain functionality while compacting the overall footprint.
2Productivity
If vertical pitch is reduced to increase memory density, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory array into multiple banks, each with its own local x-decoders stacked vertically. Each decoder handles a specific segment of word lines, allowing independent optimization and simplifying the design of individual decoder units. This segmentation enables reduced vertical pitch while managing complexity through modular organization.
Solution Approach 2:
By moving from two-dimensional planar layout to three-dimensional vertical stacking, the patent achieves higher memory density without proportionally increasing in-plane complexity. The vertical dimension provides additional space for transistor arrangements, allowing compact integration while maintaining manageable complexity through standardized vertical building blocks.
Data Source
AI summary
A two-sided memory array is disclosed. Each side includes four local x-decoders. Each local x-decoder includes: a first pair of cascode transistors coupled to a first signal; a second pair of cascode transistors coupled to the first signal, a second signal, and a word line; a third transistor coupled to the first signal; and a third pair of cascode transistors coupled to the second signal, a third signal, and the word line. All transistors in each local x-decoder are disposed vertically, and P-channels and N-channels on each side of the memory array are disposed in an order corresponding to P-channels of a first local x-decoder, P-channels of a second local x-decoder, P-channels of a third local x-decoder, P-channels of a fourth local x-decoder, N-channels of the fourth local x-decoder, N-channels of the third local x-decoder, N-channels of the second local x-decoder and N-channels of the first local x-decoder.