Locality-aware cache coherence for multi-processor systems
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Solution Overview
Problem
Conventional cache coherence mechanisms incur high overhead, especially in distributed shared-memory systems with low data sharing among processors, and fail to efficiently manage remote memory access, leading to performance degradation and increased costs due to bandwidth-intensive requirements.
Innovation Solution
A cache coherence technique that distinguishes between remote and local data, and shared and private data, using metadata to manage cache lines and optimize operations within critical sections, reducing the need for directory structures and broadcast mechanisms, and implementing a scalable, locality-aware approach for flushing and invalidating data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cache coherence mechanisms are used in distributed shared-memory systems, then memory consistency is maintained, but storage overhead and coherence overhead increase significantly
Solution Approach 1:
The patent applies local quality by differentiating between local and remote memory accesses, and between shared and private data. The cache coherence mechanism selectively applies coherence protocols only when necessary (for shared data in critical sections), rather than universally. This allows the system to maintain memory consistency for shared data while avoiding unnecessary overhead for private data, thereby reducing overall storage and coherence overhead.
Solution Approach 2:
The patent segments the memory address space into shared and private regions, and further segments cache lines into those requiring coherence monitoring and those that don't. By using metadata bits to mark cache lines as shared or private, the system can apply different coherence management strategies to different segments, reducing the burden on the coherence protocol for private data while maintaining consistency for shared data.
2Reliability
If conventional cache coherence mechanisms are used, then memory consistency is ensured, but performance degrades due to bandwidth-intensive requirements
Solution Approach 1:
The patent optimizes performance by treating local and remote memory accesses differently. Local memory accesses bypass coherence checking entirely, providing high-speed access without protocol overhead. Remote memory accesses to shared data in critical sections undergo coherence checking, while other remote accesses are optimized. This selective approach maintains memory consistency where required while maximizing performance for the majority of accesses.
Solution Approach 2:
The patent uses preliminary action by pre-marking cache lines with metadata indicating whether they contain shared or private data. This allows the coherence mechanism to make decisions based on pre-computed information rather than requiring runtime analysis, reducing latency and improving performance. The critical section detection is also performed in advance, allowing the system to prepare appropriate coherence actions before actual memory accesses occur.
3Reliability
If directory structures and broadcast mechanisms are used for cache coherence, then memory consistency is maintained, but device complexity and cost increase
Solution Approach 1:
The patent extracts the essence of cache coherence management from complex directory structures and broadcast mechanisms, retaining only the essential functionality needed for shared data. By using simple metadata bits in cache lines and event-driven invalidation for shared cache lines, the patent eliminates the need for complex global directories and broadcast protocols, significantly reducing hardware complexity while maintaining memory consistency for shared data.
Solution Approach 2:
The patent implements self-service by enabling cache lines to carry their own coherence information through metadata bits indicating shared or private status. This eliminates the need for external directory structures to track cache line ownership and sharing status. The cache coherence system serves itself using information embedded in the cache lines, reducing the need for complex external control structures.
Data Source
AI summary
A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.