Localized Fin Width Scaling via Hydrogen Anneal
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Solution Overview
Problem
Existing methods for thinning fins in FinFETs, such as oxidation, lead to physical faults and defects due to undercutting of spacers, compromising the control of short channel effects and current leakage, while reducing fin width increases effective resistance and current crowding.
Innovation Solution
A hydrogen anneal process is applied to selectively thin the channel region of semiconductor fins, preserving fin width in source and drain regions, and epitaxially growing fins in these regions to reduce leakage current without increasing exterior resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If oxidation process is used to thin fins, then fin width is reduced to improve gate control, but spacers are undercut causing physical faults and defects
Solution Approach 1:
The patent changes the chemical parameters of the annealing process by introducing hydrogen gas and controlling temperature (e.g., 400-450°C) to selectively thin fins without the harsh effects of oxidation. This parameter change allows fin thinning while preserving spacer integrity, resolving the contradiction between manufacturing precision and reliability
Solution Approach 2:
The patent uses an inert hydrogen atmosphere during the annealing process to prevent oxidative damage to spacers. The hydrogen environment enables controlled fin thinning through hydrogen diffusion and void formation without causing the oxidative undercutting that would compromise transistor integrity, thus resolving the contradiction
2Reliability
If fin width is reduced to enhance gate control, then short channel leakage decreases, but current crowding at fin exterior increases effective resistance
Solution Approach 1:
The patent applies local quality by creating non-uniform fin structures where the fin width varies along its length. The fin is thinner at the channel region (improving leakage control) and wider at the source/drain regions (reducing current crowding). This local variation in geometry allows simultaneous optimization of both leakage control and drive current, resolving the contradiction
Solution Approach 2:
The patent introduces a new dimensional aspect to fin design by creating tapered or curved fin profiles rather than uniform rectangular cross-sections. This dimensional change allows the fin to have different effective widths at different locations, enabling improved gate control at the channel while maintaining lower resistance at the contacts, thus resolving the contradiction
3Manufacturing precision
If fin width is uniformly decreased, then gate control improves, but fin uniformity and morphology deteriorate due to current crowding
Solution Approach 1:
The patent implements local quality by making the fin structure non-uniform, with different widths at different locations. The channel region has thinner fins for better gate control, while source/drain regions have wider fins for better current flow. This localized variation maintains overall fin uniformity and morphology while achieving improved gate control, resolving the contradiction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces off-state leakage current while maintaining low fin widths, improving fin uniformity and morphology, and enhancing electrical properties by smoothing fin profiles and reducing line edge roughness, thus addressing the challenges of current crowding and short channel effects.
Implementation Method 1
A hydrogen anneal process is applied to selectively thin the channel region of semiconductor fins
Implementation Method 2
the anneal helps to thin the fins in the channel region by a process that is believed to involve the diffusion of hydrogen into the silicon and the formation of voids
Implementation Method 3
improving fin uniformity and morphology, and enhancing electrical properties by smoothing fin profiles and reducing line edge roughness
Implementation Method 4
epitaxially growing fins in these regions to reduce leakage current without increasing exterior resistance
Data Source
AI summary
Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners. There is a gate stack on the channel region of the one or more semiconductor fins.