Localized Reference Cells for Resistive Memory Sensing

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Solution Overview

Problem

Resistive memory arrays face challenges in consistent data sensing due to limited tunnel magnetoresistance and high variability in resistance spread and manufacturing variations, leading to inconsistent sensing margins.

Innovation Solution

The implementation of localized reference cells with a variable resistor and a separate reference bitline, connected to sense amplifiers, which experience the same manufacturing and environmental conditions as memory cells, providing a localized reference resistance to stabilize the voltage for accurate data detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional global reference cells are used in resistive memory arrays, then the sensing operation can be performed, but the sensing margin varies significantly due to resistance spread and manufacturing variations across different locations

Engineering Contradiction:
Improvesensing margin consistencyVSAvoiddata sensing consistency
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies local quality by replacing global reference cells with localized reference cells positioned near each sense amplifier. Each reference cell experiences the same local manufacturing variations and resistance spread as its adjacent memory cells, ensuring that the reference voltage matches the local conditions. This localized approach eliminates sensing margin variations caused by global reference inconsistencies while maintaining reliable data sensing across the entire memory array.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If reference cells are placed far from memory cells, then manufacturing variations affect both equally, but the reference voltage does not match the local resistance characteristics of memory cells

Engineering Contradiction:
Improvereference voltage matchingVSAvoiddistance between reference cell and memory cell
Core Design Contradiction:
Measurement precisionVSLength of stationary object

Solution Approach 1:

The patent positions reference cells locally adjacent to each sense amplifier and memory cell, minimizing the distance between reference and memory cells. This local placement ensures that both reference cells and memory cells experience identical local manufacturing variations and resistance characteristics, enabling accurate voltage matching for precise sensing operations.

Inventive Principle:
Principle #3Local quality

3Device complexity

If sense amplifiers use a single reference voltage for the entire array, then the circuit design is simplified, but sensing accuracy deteriorates due to resistance spread across different array locations

Engineering Contradiction:
Improvereference cell architectureVSAvoidsensing accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the unified reference voltage system into multiple localized reference cells, each serving a specific sense amplifier or region. This segmentation allows each reference cell to provide an accurate local reference voltage that matches the resistance characteristics of its adjacent memory cells, thereby improving sensing accuracy without significantly increasing overall system complexity.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces sensing margin variations by ensuring that reference cells provide a localized reference voltage matching the resistance components of adjacent memory cells, enhancing data sensing consistency and accuracy.

Implementation Method 1

limited tunnel magnetoresistance (TMR) in MRAMs

Methodology Applied
Scientific EffectTunnel magnetoresistance: Magnetoresistance

Data Source

PatentUS11881241B2Resistive memory array with localized reference cells
Publication Date: 2024.01.23 GLOBALFOUNDRIES US INC
  • US11881241B2 patent drawing
  • US11881241B2 patent drawing
  • US11881241B2 patent drawing

AI summary

A structure includes an array of nonvolatile memory cells, wordlines and bitlines connected to the nonvolatile memory cells, sense amplifiers connected to the nonvolatile memory cells, and reference cells connected to the sense amplifiers. Each of the reference cells has a transistor connected to a variable resistor, one of the wordlines, a reference bitline separate from the bitlines, and the sense amplifiers.