Localized SOI Superlattice Structure for Higher Carrier Mobility
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Solution Overview
Problem
Current semiconductor devices lack enhanced performance due to limitations in carrier mobility and interface quality, which affects device speed and power consumption.
Innovation Solution
The implementation of a semiconductor device with localized semiconductor-on-insulator (SOI) regions and a superlattice structure, comprising stacked groups of semiconductor and non-semiconductor monolayers, which reduces effective mass and improves interface quality, thereby enhancing charge carrier mobility and providing piezoelectric, pyroelectric, and ferroelectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor structures are used, then manufacturing simplicity is maintained, but carrier mobility and device performance are limited
Solution Approach 1:
The semiconductor structure is segmented into distinct regions: bulk semiconductor regions and localized SOI regions with semiconductor layers on buried insulator regions. This segmentation allows different functional characteristics in different areas, improving overall device performance while maintaining manageable complexity through modular design
Solution Approach 2:
The patent implements local quality by creating localized SOI regions with specific semiconductor layers only where needed, while other areas maintain bulk semiconductor properties. This allows optimization of carrier mobility and interface quality in specific device regions without complicating the entire wafer structure
2Speed
If semiconductor layers on buried insulator regions are implemented, then carrier mobility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent applies partial action by implementing semiconductor layers on buried insulator regions only in localized areas rather than across the entire wafer. This partial implementation enhances carrier mobility where needed while avoiding the full manufacturing complexity of complete SOI structures
Solution Approach 2:
The patent changes physical parameters by introducing buried insulator regions and thin semiconductor layers that modify carrier transport properties. These parameter changes enhance mobility and reduce scattering effects while the localized implementation keeps manufacturing complexity manageable
3Reliability
If superlattice structures are introduced, then interface quality and carrier mobility improve, but device complexity increases
Solution Approach 1:
The superlattice structure is implemented locally within the semiconductor layers on buried insulator regions rather than throughout the entire device. This localized application improves interface quality and carrier mobility at critical interfaces while maintaining simpler bulk regions elsewhere
Solution Approach 2:
The patent uses composite material structures by combining semiconductor layers with buried insulator regions and superlattice configurations. These composite structures improve interface quality and reduce scattering effects while the modular composite design manages overall device complexity
4Productivity
If localized bulk and SOI regions are integrated on the same wafer, then manufacturing efficiency improves, but device uniformity becomes more difficult to control
Solution Approach 1:
The wafer is segmented into distinct bulk and localized SOI regions that can be manufactured using similar processes. This segmentation allows integration of different device types on the same wafer, improving manufacturing efficiency while maintaining controllable uniformity within each region type
Solution Approach 2:
The patent implements universality by using a common manufacturing process platform that can produce both bulk and SOI devices on the same wafer. This multi-functional approach improves manufacturing efficiency while standardized processes help maintain device uniformity across different region types
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to increased charge carrier mobility, reduced scattering effects, and improved device performance, making it suitable for high-speed, low-power devices and opto-electronic applications, while also allowing for integration of both bulk and SOI devices on the same wafer, reducing manufacturing costs.
Implementation Method 1
a superlattice in the monocrystalline semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Implementation Method 2
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 3
Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility
Data Source
AI summary
A semiconductor device may include a semiconductor substrate, buried spaced-apart insulator regions in the substrate, and a monocrystalline semiconductor layer on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions. The semiconductor device may also include a superlattice in the monocrystalline semiconductor layer. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include semiconductor devices in the monocrystalline layer, with at least some of the semiconductor devices in the localized SOI regions, and at least some other semiconductor devices in the localized bulk semiconductor regions.