Localized SOI CMOS Structure for Leakage and Latch-Up Control
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Solution Overview
Problem
The high cost of traditional Silicon on Insulator (SOI) wafers and the challenges of leakage current, latch-up issues, and floating body effect in CMOS circuits, which hinder the adoption of SOI technology for cost-effective and high-performance integrated circuits.
Innovation Solution
The development of a CMOS circuit using a Single-Crystalline Silicon Island On Insulator (SC-SIOI) structure within a bulk semiconductor substrate, eliminating the need for an entire SOI wafer, with localized isolating layers under PMOS and NMOS transistors to reduce leakage currents and latch-up concerns, and partially isolating the NMOS transistor body from the bulk substrate to address the floating body effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SOI wafer is used to fabricate CMOS circuit, then leakage current and latch-up issues are reduced, but fabrication cost increases significantly
Solution Approach 1:
The patent divides the SOI structure into segmented regions: fully-depleted SOI regions under PMOS transistors and partially-depleted SOI regions under NMOS transistors. This segmentation allows different isolation depths to be implemented in different areas of the CMOS circuit, optimizing both leakage reduction and cost efficiency.
Solution Approach 2:
The patent applies different isolation qualities to different transistor types: PMOS transistors receive full SOI isolation (deeper isolating layer) to maximize leakage reduction, while NMOS transistors receive partial SOI isolation (shallower isolating layer) to balance performance and cost. This local differentiation resolves the contradiction by tailoring isolation strength to specific device requirements.
2Reliability
If fully-depleted SOI structure is used for both PMOS and NMOS transistors, then leakage current is minimized, but floating body effect occurs in NMOS transistors
Solution Approach 1:
The patent implements different isolation depths for PMOS and NMOS transistors: deeper isolation for PMOS to minimize leakage, and shallower isolation for NMOS to prevent floating body effect. This local quality differentiation allows each transistor type to have optimized isolation characteristics suitable for its specific electrical behavior.
Solution Approach 2:
The SOI isolating layer is segmented into two distinct depth regions: a first depth for PMOS transistors that fully depletes the body to reduce leakage, and a second (shallower) depth for NMOS transistors that maintains body connection to prevent floating body effects. This segmentation resolves the contradiction by spatially separating the isolation strategies.
3Manufacturing precision
If ion-implantation process is used to dope Source/Drain regions, then doping precision is improved, but process complexity and cost increase
Solution Approach 1:
The patent replaces the ion-implantation process (mechanical/physical system) with a chemical vapor deposition (CVD) process that uses gaseous precursors to deposit doped silicon layers. This substitution eliminates the complexity of ion implantation equipment and process control while achieving comparable doping precision through chemical vapor phase reactions.
Solution Approach 2:
The patent changes the fundamental parameter of the doping process from physical ion bombardment to chemical vapor deposition. By using gaseous silicon sources with controlled decomposition and deposition parameters, the process achieves precise doping concentrations and profiles without the complexity of ion acceleration, focusing, and implantation control.
Data Source
AI summary
A complementary metal-oxide-semiconductor (CMOS) circuit includes a bulk semiconductor substrate, a first active region and a second active region, a first type transistor, a first localized isolating layer, a second type transistor, and a second localized isolating layer. The bulk semiconductor substrate has an original semiconductor surface. The first active region and the second active region are formed based on the bulk semiconductor substrate. The first type transistor is formed based on the first active region and has a first doped body. The first localized isolating layer is under the first type transistor and at least isolates the first doped body from the bulk semiconductor substrate. The second type transistor is formed based on the second active region and has a second doped body. The second localized isolating layer is under the second type transistor and at least partially isolates the second doped body from the bulk semiconductor substrate.