Localized SOI Region Structure for Low-Cost Electrical Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for achieving electrical isolation between a semiconductor substrate and devices formed on it, such as using p-n junctions or semiconductor-on-insulator wafers, face challenges like device failures due to p-n junction breakdowns and high costs associated with forming semiconductor-on-insulator wafers.
Innovation Solution
A semiconductor structure with a bulk semiconductor substrate and a semiconductor-on-insulator region, where the upper semiconductor layer is physically separated from the substrate by insulator-containing cavities, and optionally a lower semiconductor layer, formed through a process involving selective isotropic etching and amorphization/recrystallization to ensure electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor-on-insulator wafers are used to achieve electrical isolation, then device reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent divides the semiconductor structure into distinct regions: bulk substrate regions and localized semiconductor-on-insulator regions. This segmentation allows electrical isolation to be applied only where needed rather than across the entire wafer, reducing manufacturing costs while maintaining device reliability in critical areas.
Solution Approach 2:
The patent implements electrical isolation locally through selectively formed insulator-containing cavities and plugs only in specific regions where devices require enhanced isolation. The bulk substrate retains its original structure in non-critical areas, optimizing the balance between reliability and manufacturing cost.
2Reliability
If semiconductor-on-insulator wafers are used to prevent p-n junction breakdown, then device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the isolation implementation into discrete steps: forming openings, creating insulator-containing cavities through selective etching, and depositing plugs. This segmented approach simplifies the overall manufacturing process compared to forming complete semiconductor-on-insulator wafers, while still preventing p-n junction breakdown in critical regions.
Solution Approach 2:
The patent performs preliminary actions by forming the insulator-containing cavities and plugs before final device fabrication. This preliminary isolation structure prevents future p-n junction breakdowns and simplifies subsequent manufacturing steps by eliminating the need for complex post-processing isolation techniques.
3Ease of manufacture
If p-n junctions are used for electrical isolation, then manufacturing cost is reduced, but device reliability deteriorates due to breakdown risk
Solution Approach 1:
The patent applies enhanced electrical isolation using insulator-containing cavities and plugs only in regions where devices are susceptible to p-n junction breakdown. In less critical areas, simpler isolation methods can be used, maintaining cost-effectiveness while improving reliability where needed.
Solution Approach 2:
The patent introduces insulator-containing cavities and plugs as intermediary structures between the bulk substrate and upper semiconductor layers. These intermediaries provide enhanced electrical isolation that prevents p-n junction breakdown without requiring complete semiconductor-on-insulator wafer fabrication, thus maintaining cost advantages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides effective electrical isolation without the high costs of semiconductor-on-insulator wafers and is adaptable to devices that do not require enhanced isolation, enhancing the reliability and cost-effectiveness of semiconductor device fabrication.
Implementation Method 1
performing a selective isotropic etch process to form cavities that extend laterally off the sides of the openings into the sacrificial semiconductor layer
Implementation Method 2
amorphization/recrystallization to ensure electrical isolation
Implementation Method 3
amorphization/recrystallization to ensure electrical isolation
Data Source
AI summary
Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.