Localized SOI Structure Formation in Semiconductor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and manufacturing limitations of one-transistor (1-T) dynamic random access memory (DRAM) on silicon on insulator (SOI) wafers, which require embedded implementation due to the increased cost and unverified properties of SOI wafers, hinder standalone production.
Innovation Solution
A semiconductor device manufacturing method that forms a localized silicon on insulator (SOI) structure in one or more regions of a bulk substrate using selective etching, creating floating body patterns and filling the regions with insulating material to separate substrate and floating body regions, allowing for the formation of memory cells with improved sensing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI wafer is used for 1-T DRAM manufacturing, then sensing margin is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies local quality by forming SOI structures only in specific regions where memory cells are located, rather than using SOI wafers for the entire substrate. This is achieved through selective etching of the bulk substrate in memory cell regions while leaving the substrate intact in circuit regions, thereby obtaining the sensing margin benefits of SOI where needed while avoiding the high cost of complete SOI wafer usage.
Solution Approach 2:
The patent segments the substrate into different regions with different structures: memory cell regions with SOI structures (floating body regions separated from substrate by insulating regions) and circuit regions with bulk substrate. This segmentation allows different parts of the device to have optimized properties for their specific functions while using cost-effective bulk substrate for non-critical areas.
2Reliability
If SOI wafer is used for 1-T DRAM manufacturing, then sensing margin is improved, but device complexity increases
Solution Approach 1:
The patent introduces structural complexity (SOI structures with insulating regions) only in memory cell regions where it is needed for improved sensing margin, while keeping circuit regions as simple bulk substrate structures. This localized approach minimizes overall device complexity while achieving the required performance improvement in critical areas.
3Ease of manufacture
If selective etching is used to form localized SOI structures, then manufacturing cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by forming a patterned resist mask before the selective etching process. This mask defines the exact regions where SOI structures should be formed and protects other areas from etching. The preliminary masking step ensures that the subsequent selective etching process achieves the required precision without needing extremely advanced etching capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces manufacturing costs and enables standalone production of 1-T DRAM by forming localized SOI structures, allowing for different bias voltages to be applied to memory cells and driving circuits, preventing or reducing latch phenomena.
Implementation Method 1
dividing the region of the bulk substrate into a lower bulk substrate region and a floating body region by etching lower regions of the one or more floating body patterns
Implementation Method 2
filling a region between the floating body region and the lower bulk substrate region with an insulating material
Data Source
AI summary
Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.