Localized Spacer for Multi-Gate Transistor Leakage

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Solution Overview

Problem

Double gate transistors face challenges in forming self-aligned tip spacers to prevent undesired off-state leakage due to tip implants into non-gated or channel regions, which can cause diffusion issues.

Innovation Solution

The implementation of self-aligned tip spacers in a multi-gate transistor structure using a silicon-on-insulator (SOI) structure, where nitride spacers act as masks to prevent implantation into specific areas, allowing angled diffusion of tip material, thereby protecting the channel region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If tip implants are performed in double gate transistors, then source and drain regions can be formed, but tip material diffuses into non-gated or channel regions causing undesired off-state leakage

Engineering Contradiction:
Improvetip implant formationVSAvoidoff-state leakage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Nitride spacers are formed on the sidewalls of the SOI structure before tip implantation. These spacers serve as preliminary protective barriers that prevent tip material from diffusing into the channel region during subsequent implantation processes, thereby eliminating off-state leakage while allowing proper source and drain formation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The nitride spacers act as intermediary protective layers between the tip implant source and the channel region. They physically block the diffusion path of tip material, preventing harmful interactions while allowing the implantation process to proceed for source and drain region formation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If nitride spacers are used to mask SOI structure, then implantation into channel region is prevented, but manufacturing process complexity increases

Engineering Contradiction:
Improvechannel region protectionVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The nitride spacers are formed using self-aligned processes where the spacers automatically position themselves on the sidewalls of the SOI structure. This self-alignment eliminates the need for additional alignment steps and complex photolithography processes, reducing manufacturing complexity while ensuring precise channel region protection

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If angled diffusion is performed for tip implantation, then source and drain regions are properly formed, but tip material may still diffuse into non-gated regions

Engineering Contradiction:
Improvesource and drain formationVSAvoidimplantation location control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The nitride spacers provide localized protection specifically at the channel region boundaries where tip material diffusion is most problematic. The spacers are positioned only where needed to block diffusion paths, while allowing angled implantation to proceed uninterrupted in the source and drain regions, thus maintaining manufacturing precision without sacrificing ease of manufacture

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces zero or reduced diffusions under the spacers, ensuring pure silicon remains in the SOI portion and preventing implantation into the channel region, thus minimizing off-state leakage and enhancing transistor performance.

Implementation Method 1

nitride spacers act as masks to prevent implantation into the area under them

Methodology Applied
Scientific EffectPhysical masking:

Implementation Method 2

diffusions that are performed to implant tip material can occur at an angle such as a 45° angle

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS8390040B2Localized spacer for a multi-gate transistor
Publication Date: 2013.03.05 TAHOE RES LTD
  • US8390040B2 patent drawing
  • US8390040B2 patent drawing
  • US8390040B2 patent drawing

AI summary

In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed.