Localized High-Density Substrate Routing for Chip-to-Chip Bandwidth
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Solution Overview
Problem
Existing multichip package substrates face challenges in achieving high-density routing due to limitations in lithography and plating processes, resulting in lower routing densities and decreased system and power performance.
Innovation Solution
Incorporating a high-density interconnect element with chip-level routing embedded in a substrate medium, allowing for localized high-density routing that can be aligned independently and unified with conventional low-density routing, enabling high-bandwidth chip-to-chip interconnects without requiring significant changes to the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional substrate routing is used, then manufacturing cost is reduced and fabrication process is simplified, but routing density and bandwidth are limited
Solution Approach 1:
The substrate is divided into multiple routing density regions, with high-density routing areas and low-density routing areas. This segmentation allows each region to be optimized independently for its specific routing density requirements without affecting the entire substrate, resolving the contradiction between achieving high routing density and maintaining fabrication simplicity.
Solution Approach 2:
Different routing density characteristics are applied to different regions of the substrate based on local performance requirements. High-density interconnect elements are placed only in areas where high bandwidth is needed, while other areas use conventional lower-density routing, allowing manufacturing processes to be simplified in non-critical areas while achieving high density where required.
2Productivity
If high-density interconnect elements are integrated throughout the substrate, then system performance and bandwidth are improved, but manufacturing cost and fabrication complexity increase
Solution Approach 1:
High-density interconnect elements are integrated only in specific regions where high bandwidth is required, rather than uniformly across the entire substrate. This localized approach improves system performance in critical areas while avoiding the increased fabrication complexity and cost that would result from implementing high-density routing throughout the entire substrate.
Solution Approach 2:
The substrate is segmented into regions with different routing density requirements. High-density interconnect elements are placed in specific segments where performance demands justify the increased complexity, while other segments use conventional routing techniques, thereby achieving improved bandwidth without proportionally increasing overall fabrication complexity.
3Ease of manufacture
If uniform routing density is maintained across the substrate, then fabrication process is simplified, but areas requiring high-density routing cannot achieve sufficient bandwidth
Solution Approach 1:
The substrate is designed with varying routing density characteristics in different regions, allowing areas with high performance requirements to achieve sufficient bandwidth through high-density routing, while other areas use simpler conventional routing. This local differentiation maintains fabrication simplicity in non-critical areas while ensuring system performance requirements are met in critical regions.
Data Source
AI summary
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.