Location-Aware Global Cache Tiering for Lower Transfer Latency

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Solution Overview

Problem

Existing distributed storage systems face inefficiencies in data caching due to the lack of consideration for the geographical location of storage devices and processors, leading to suboptimal data transfer times and resource utilization.

Innovation Solution

Implementing a cache metadata table that includes location identifiers for cache slots, allowing for location-based allocation of cache slots using direct memory access (DMA) commands, and utilizing a global memory cache that spans multiple storage processors or computing devices, prioritizing cache allocation based on proximity and subscription plans.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If cache slots are allocated without considering geographical location, then cache allocation is simple and fast, but data transfer latency increases and resource utilization decreases

Engineering Contradiction:
Improvedata transfer latencyVSAvoidcache allocation complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system pre-populates the cache metadata table with location identifiers for each cache slot before actual caching operations begin. This preliminary organization of spatial information enables location-based cache slot selection without adding complexity to the real-time cache allocation process, thereby reducing data transfer latency while maintaining efficient resource utilization

Inventive Principle:
Principle #10Preliminary action

2Productivity

If a global memory cache table is implemented across multiple storage processors, then resource utilization improves, but system complexity and coordination overhead increase

Engineering Contradiction:
Improveresource utilizationVSAvoidsystem coordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The global memory cache table is segmented into distributed cache metadata tables across multiple storage processors. Each storage processor maintains its own cache metadata table with local cache slot information, while the system provides unified global address space through consistent address mapping. This segmentation allows parallel cache operations across multiple processors without requiring complex centralized coordination, thereby improving resource utilization while controlling system complexity

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If cache slots are distributed across multiple physical locations, then system scalability improves, but data transfer efficiency decreases due to remote access

Engineering Contradiction:
Improvesystem scalabilityVSAvoiddata transfer speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The system implements location-aware cache slot selection that prioritizes cache slots located in the same physical location or closer proximity to the requesting node. The cache metadata table includes location identifiers that enable the system to select the nearest available cache slot, ensuring that frequently accessed data is cached in geographically proximate locations. This local quality approach maintains high data transfer speeds while allowing the system to scale by adding cache slots at multiple locations

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250307141A1Location-based global cache tiering
Publication Date: 2025.10.02 DELL PROD LP
  • US20250307141A1 patent drawing
  • US20250307141A1 patent drawing
  • US20250307141A1 patent drawing

AI summary

A method for use in a storage processor, comprising: generating or updating a cache metadata table that identifies a plurality of cache slots, for each of the plurality of cache slots, the cache metadata table including a different respective location identifier that indicates a location for that cache slot; receiving an I/O request that is associated with a logical block address; allocating a given one of the plurality of cache slots to the logical block address based on the respective location identifier that corresponds to the given cache slot; and executing the I/O request by using the given cache slot, wherein using the given cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command based on the memory address.