Location-Based NoC Subtopologies for SoC Wire Delay Reduction
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Solution Overview
Problem
As microprocessors handle larger and more complex workloads, traditional network-on-chip (NoC) topologies face limitations due to long wire delays and dense logic, which can lead to performance bottlenecks and timing issues in system-on-chip (SoC) designs.
Innovation Solution
The implementation of a location-based NoC interface with subtopologies, where the NoC topology is divided into subtopologies based on the physical location of logic blocks, each including at least one router. This approach optimizes the placement and coupling of subtopologies using communications protocols, enabling efficient data transfer between logic blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single NoC topology is used to connect all logic blocks, then the communication infrastructure is simple, but long wire delays and performance bottlenecks occur
Solution Approach 1:
The patent divides the single NoC topology into multiple subtopologies based on the physical location of logic blocks. Each subtopology serves a specific region or functional unit, reducing the maximum communication distance within each subtopology and thereby decreasing wire delays while maintaining overall system connectivity.
Solution Approach 2:
The patent introduces a hierarchical dimension to the NoC architecture by organizing subtopologies into groups and levels. This multi-level hierarchy allows communication to occur at different scales - local communication within subtopologies and global communication between them - effectively reducing the time penalty of long-distance wires through dimensional organization.
2Area of stationary object
If logic blocks are densely packed to increase chip capacity, then area efficiency improves, but communication paths become congested and timing issues arise
Solution Approach 1:
The patent applies local quality by creating subtopologies with specialized characteristics suited to their specific regions or functional units. Each subtopology can be optimized for its local communication patterns and timing requirements, allowing dense packing while maintaining reliable timing through location-aware design.
3Speed
If the NoC topology is optimized for current performance, then communication speed improves, but adaptability to future scaling and new configurations is reduced
Solution Approach 1:
The patent creates a dynamic and flexible NoC architecture where subtopologies can be independently configured, added, or modified based on evolving requirements. The hierarchical structure and location-based organization allow the system to adapt to future scaling and new configurations while maintaining optimized communication paths for current performance needs.
Data Source
AI summary
Disclosed embodiments provide techniques for a networking with a network-on-chip (NoC) interface with subtopologies. A system-on-chip (SoC) is accessed. The SoC includes a plurality of logic blocks. A NoC topology is created. The NoC topology includes one or more subtopologies. The one or more subtopologies are based on a physical location of the plurality of logic blocks. Each subtopology includes at least one router. A location of the one or more subtopologies is optimized. The one or more subtopologies are coupled based on one or more communications protocols. A protocol running on the plurality of logic blocks is translated to the one or more communications protocols. Data is sent from a sending subtopology within the one or more subtopologies to a receiving subtopology within the one or more subtopologies.