Parallel Byte Error Correction with Locator Polynomial Circuits
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Solution Overview
Problem
Existing solutions for correcting byte errors, particularly in memory cells like MRAM and RRAM, are slow and inefficient, especially when dealing with multiple byte errors.
Innovation Solution
A circuit arrangement is proposed that determines byte error position signals and correction values using a locator polynomial, allowing for parallel correction of byte errors in multiple bytes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Reed-Solomon code is used for correcting 2-byte errors as described in OKANO, then error correction capability is improved, but correction speed deteriorates
Solution Approach 1:
The patent segments the error correction process into independent parallel operations for each byte position. Instead of processing bytes sequentially as in conventional Reed-Solomon decoders, the invention calculates error position signals and correction values for multiple byte positions simultaneously using separate processing paths, thereby achieving parallel execution and improved correction speed while maintaining the ability to correct 2-byte errors
Solution Approach 2:
The patent performs preliminary calculation of error position signals and correction values before the actual error correction is needed. By pre-computing these parameters using the locator polynomial and syndrome values, the system prepares correction data in advance, allowing rapid application of corrections when errors are detected, thus improving overall correction speed
2Speed
If parallel error correction is implemented for multiple bytes, then correction speed is improved, but device complexity increases
Solution Approach 1:
The patent employs universal processing units that can handle multiple byte positions with the same operational logic. The error position signal generation and correction value calculation circuits are designed to be replicated and applied to different byte positions, allowing parallel processing through standardized modular blocks rather than custom complex circuits for each byte, thus managing device complexity while achieving parallelism
Solution Approach 2:
The patent transitions from sequential single-byte processing to multi-dimensional parallel processing by introducing additional processing dimensions. Instead of one processing path handling bytes one after another, the invention creates multiple independent processing paths operating simultaneously in parallel, effectively adding a temporal dimension to the correction process and achieving speedup through dimensional expansion of the computational space
Data Source
AI summary
An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.