Error Correction Circuit Using Locator Polynomials for 4-Bit+ Decoding
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Solution Overview
Problem
Existing error correction methods, such as BCH codes, are inefficient in correcting errors beyond 3-bit errors due to complex decoding processes and high circuitry requirements, and cannot correct t-bit errors where t>4.
Innovation Solution
A circuit arrangement is developed that uses subcircuits to determine correction signals based on locator polynomial values and error signals, allowing for the correction of t-bit errors greater than 4 by logically combining bit positions and correction values, and utilizing a selection unit and concentrating unit to efficiently process error syndromes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BCH codes are used to correct arbitrary 1-bit, 2-bit and 3-bit errors in parallel using combinational error correction circuits, then error correction capability for up to 3-bit errors is achieved, but the capability to correct more than 3-bit errors is limited
Solution Approach 1:
The patent divides the error correction task into multiple subcircuits, each responsible for a specific bit position. Each subcircuit independently processes locator polynomial values for its assigned bit position, enabling parallel correction of multiple bit errors simultaneously. This segmentation allows the system to scale error correction capability beyond the traditional 3-bit limit by adding more subcircuits for additional bit positions.
2Reliability
If a fourth-degree equation is solved to correct 4-bit errors by reducing it to two second-degree equations, then 4-bit error correction is achieved, but the decoding becomes slow and requires high outlay on circuitry
Solution Approach 1:
The patent segments the complex polynomial solving task into multiple independent subcircuits, each handling a specific bit position. This division allows parallel processing of error correction calculations, significantly reducing the time required compared to sequential solution of high-degree equations.
Solution Approach 2:
The patent pre-calculates and stores locator polynomial values for each bit position in lookup tables before error correction is needed. When an error occurs, the system simply retrieves pre-computed values and combines them using XOR operations, eliminating the need for complex real-time polynomial solving and reducing both circuit complexity and decoding time.
3Reliability
If existing error correction methods are used, then correction of up to 3-bit errors is possible, but correction of t-bit errors where t>4 cannot be achieved
Solution Approach 1:
The patent creates a universal error correction architecture where the same subcircuit design can correct any number of bit errors by simply adding more subcircuits. Each subcircuit is multi-functional, capable of handling different error scenarios (1-bit, 2-bit, 3-bit, 4-bit or more) by selecting appropriate locator polynomial values from lookup tables. This universal design eliminates the need for separate correction mechanisms for different error magnitudes.
Solution Approach 2:
The patent implements a dynamic error correction system where the number of correctable bits can be adjusted by configuring the number of subcircuits and selecting different locator polynomial values. The system adapts to different error scenarios in real-time by dynamically selecting which locator polynomial values to use based on the error pattern detected, enabling flexible correction of t-bit errors where t>4.
Data Source
AI summary
A circuit arrangement for determining a correction signal on the basis of at least one bit error of a binary word is specified, including a plurality of subcircuits (ST), wherein a respective subcircuit is provided for a bit position to be corrected of the binary word, wherein each of the subcircuits provides at least two locator polynomial values, and comprising a selection unit, which determines a correction signal depending on the locator polynomial values and depending on an error signal (err, E). A method for driving such a circuit arrangement is furthermore proposed.