Lock-Access Message for Persistent Memory Latency
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Solution Overview
Problem
In rack-scale computer systems with global persistent memory, existing locking mechanisms require multiple messages for locking and unlocking data objects, leading to increased latency due to the high number of messages exchanged between nodes and the memory fabric, especially in systems with thousands of nodes and petabytes of shared memory.
Innovation Solution
The introduction of lock-access and access-unlock messages that combine the request for memory access operations with locking or unlocking operations in a single message, reducing the number of messages needed by using memory capabilities to manage access and locking of data objects directly with the memory-side accelerator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional locking mechanisms are used with multiple separate messages for locking and unlocking operations, then the locking and unlocking functionality is reliable and well-defined, but the latency increases due to the high number of messages exchanged between nodes and the memory fabric
Solution Approach 1:
The patent combines locking and memory access operations into a single lock-access message, and unlocking and memory access operations into a single access-unlock message. This merging of operations reduces the number of messages exchanged between computing nodes and the memory fabric, directly addressing the latency issue while maintaining the reliability of locking functionality through the memory-side accelerator's capability to handle these combined operations atomically
2Productivity
If the number of messages exchanged between nodes and memory fabric is reduced by combining operations, then the latency decreases and system performance improves, but the complexity of message handling at the memory-side accelerator increases
Solution Approach 1:
The memory-side accelerator acts as an intermediary that receives lock-access and access-unlock messages containing memory capabilities, validates them, and performs the appropriate locking/unlocking operations before executing memory access operations. This intermediary handles the complexity of combined operations centrally, allowing computing nodes to send simpler combined messages while maintaining improved system performance
3Loss of time
If lock-access and access-unlock messages are used to combine operations, then the number of messages is reduced by 50% for N=2, 40% for N=3, and 33% for N=4 access operations, but the requirement for memory capabilities and their validation adds complexity to the system
Solution Approach 1:
Memory capabilities are created and validated in advance before the actual memory access operations. The memory-side accelerator validates these pre-created capabilities when receiving lock-access or access-unlock messages, which reduces the validation overhead during critical path operations and enables the message reduction benefits while managing the complexity of capability validation
Data Source
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AI summary
An example computing system may include a plurality of processors, persistent memory that is shared by the plurality of processors, and a memory-side accelerator that is to control access to the memory. A requesting processor of the plurality of processors may simultaneously request locking of and access to a target data object of the persistent memory by sending a single lock-and-access message to the memory-side accelerator. The lock-and-access message may include a first memory capability pointing to the target data object, a second memory capability pointing to a lock object that controls locking of the target data object, and a specified access operation that is requested. The memory-side accelerator may, in response to receiving the lock-and-access message: fetch locking information that is stored in the lock object pointed to by the second memory capability, and determine, based on the locking information, whether to lock and perform the requested access operation on the target data object pointed to by the first memory capability for the requesting processor.