Lock Address Contention Table for Semaphore Cache Coherency
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Solution Overview
Problem
Contended semaphores in multi-core systems generate undesirable cache coherency traffic and high latencies due to unnecessary cache line transmissions during semaphore acquisition and release.
Innovation Solution
Each core maintains a lock address contention table to track the state of contended lock instructions, allowing it to respond with negative acknowledgments when a semaphore is acquired in an exclusive state, thereby avoiding unnecessary cache line transmissions and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache coherency protocols are used for contended semaphores, then cache line transmissions occur during semaphore acquisition and release, but this generates undesirable cache traffic and high latencies
Solution Approach 1:
The patent extracts the problematic cache coherency traffic by introducing a special handling mechanism for semaphore addresses. When a semaphore is detected as contended, the system takes out the unnecessary cache line transmissions from the normal cache coherency protocol flow, allowing semaphore operations to proceed without generating spurious cache traffic to other cores.
Solution Approach 2:
Instead of allowing cache lines to be transmitted to all cores and then invalidating them (traditional approach), the patent inverts the approach by preventing the transmission in the first place for semaphore addresses. The cache coherency protocol is made asymmetric: normal memory addresses receive full cache coherency treatment, while semaphore addresses are excluded from generating cache traffic.
2Reliability
If cache lines are transmitted to all cores during semaphore operations, then cache coherency is maintained, but unnecessary cache traffic increases
Solution Approach 1:
The patent extracts semaphore addresses from the set of addresses that trigger cache coherency traffic. By identifying and separating semaphore operations from normal memory operations, the system prevents energy-wasting cache line transmissions to cores that do not need them, while still maintaining cache coherency for actual data accesses.
3Reliability
If traditional semaphore acquisition is used, then mutual exclusion is achieved, but high latencies occur due to cache traffic
Solution Approach 1:
The patent introduces an intermediary mechanism (the cache coherency protocol modification) that mediates between semaphore operations and cache traffic generation. This intermediary layer detects semaphore addresses and intercepts the cache coherency protocol to prevent unnecessary transmissions, thereby speeding up semaphore acquisition while still ensuring mutual exclusion through the atomic compare-and-swap operation.
Data Source
AI summary
The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.