Loss-of-Lock Detector Circuit Using PFD Error Pulse Integration
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Solution Overview
Problem
Conventional clock and data recovery circuits (CDRs) face challenges in accurately determining when a clock signal is locked to an incoming data signal, particularly due to the limitations of rotational frequency detectors and unilateral lock detectors, which can lead to incorrect frequency locking and failure to detect loss of lock once locked, and are inefficient in terms of space, power, and component usage.
Innovation Solution
The proposed solution involves a system and method that includes a phase-frequency detector (PFD) circuit, a voltage-controlled oscillator (VCO), and a loss of lock detector (LOL) with a logic gate, voltage-to-current converter, capacitor, and comparator, which perform an AND function on UP and DOWN error signals to generate a lock signal, indicating whether the clock signal is locked to the data signal based on the pattern of these signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional rotational frequency detectors or unilateral lock detectors are used, then the device complexity is reduced, but the reliability of lock detection deteriorates due to incorrect frequency locking and failure to detect loss of lock
Solution Approach 1:
The lock detection function is segmented into multiple independent components: an AND gate that processes UP and DOWN error signals, a voltage-to-current converter that transforms the digital AND output to current, a capacitor that integrates the current to produce a DC voltage, and a comparator that thresholds the DC voltage to generate the final lock signal. This segmentation allows each component to perform a specific function reliably, improving overall detection accuracy while using simple, well-understood circuit elements.
Solution Approach 2:
The patent introduces intermediate signal processing stages between the error signals and the final lock detection output. The AND gate acts as an intermediary that combines UP and DOWN signals to create a new intermediate signal that is then converted to current, integrated to DC voltage, and finally thresholded. These intermediary transformations improve reliability by creating a more robust detection mechanism that is less susceptible to errors in the raw error signals.
2Loss of energy
If conventional lock detectors are used, then the device is simpler, but the power consumption increases due to inefficient circuit design
Solution Approach 1:
The patent replaces traditional complex lock detection mechanisms with a streamlined electronic circuit system. Instead of using sophisticated digital signal processing or multiple comparator stages, the invention uses a simple sequence of electronic components: an AND gate, voltage-to-current converter, integrating capacitor, and single comparator. This substitution dramatically reduces power consumption while maintaining detection functionality, as each component is a low-power standard electronic element.
3Ease of manufacture
If conventional frequency detectors are used, then the component count is reduced, but the manufacturing cost increases due to use of costly specialized components
Solution Approach 1:
The patent employs inexpensive, readily available electronic components throughout the lock detection circuit. The AND gate, voltage-to-current converter, capacitor, and comparator are all standard, low-cost items that can be easily manufactured and integrated. This approach eliminates the need for expensive specialized frequency detector ICs or complex integrated circuits, making the system economically manufacturable while achieving reliable lock detection through proper circuit architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate and efficient locking of the clock signal to the data signal, quickly detecting loss of lock, and reducing the need for costly components and power consumption, thereby enhancing the reliability and efficiency of communication systems.
Implementation Method 1
The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal
Implementation Method 2
The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses
Data Source
AI summary
A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a comparator coupled to the capacitor. The logic gate is configured to receive a first error signal and a second error signal from a phase detector, perform an AND function of the first and second error signals, and generate a gate output signal. The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal. The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses. The comparator is configured to compare the DC signal to a reference signal and output a lock signal.