Lock-Free Dual Queue Condition Synchronization

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Solution Overview

Problem

Current lock-free dual queue designs face issues such as excessive CPU usage due to busy-wait implementations and the inability to set time limits for thread waits, leading to inefficiencies in multiprocessor systems.

Innovation Solution

A lock-free dual queue method utilizing condition synchronization primitives, where threads wait on unique condition variables for data additions, allowing for efficient and timed operations without exclusive access, thus eliminating contention and overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If busy-wait implementation is used in lock-free dual queue, then threads can continuously check for data availability, but CPU usage increases excessively

Engineering Contradiction:
Improvedata availability detectionVSAvoidCPU usage
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent introduces condition variables as intermediary objects that mediate between threads waiting for data and threads producing data. Instead of continuous polling (busy-waiting), waiting threads call wait() on their condition variable, which puts them to sleep efficiently. The producing thread signals the condition variable when data is available, waking up waiting threads. This intermediary mechanism eliminates CPU-wasting busy-waiting while maintaining reliable data availability detection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical busy-wait polling mechanism with an event-driven notification system using condition variables and signals. Instead of continuously checking (mechanical repetition), the system uses asynchronous notification where the producing thread actively notifies waiting threads through condition variable signals. This substitution transforms the approach from active continuous checking to passive event-driven waiting, dramatically reducing CPU usage.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If lock-free design is used, then concurrent access without exclusive locking is achieved, but condition synchronization and timed waits are difficult to implement

Engineering Contradiction:
Improveconcurrent access efficiencyVSAvoidsynchronization mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the synchronization mechanism into separate components: condition variables for each thread, signals for notification, and timeout handling as distinct operations. Each thread has its own condition variable and can independently wait with or without timeout. This segmentation allows the lock-free queue to maintain high concurrent access efficiency while providing flexible synchronization and timed wait capabilities through modular, manageable components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameters of the wait operation by introducing optional timeout values and different wait modes (with timeout, without timeout, spinnable). The condition variable wait mechanism accepts parameter variations such as timeout durations and notification types. This parameter flexibility allows the same lock-free queue structure to support multiple synchronization scenarios without increasing fundamental complexity, resolving the contradiction between concurrent efficiency and synchronization capability.

Inventive Principle:
Principle #35Parameter changes

3Speed

If threads continuously poll for data in lock-free queue, then data availability is quickly detected, but CPU cycles are wasted

Engineering Contradiction:
Improvedata detection speedVSAvoidCPU cycles
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent replaces continuous periodic polling with event-triggered periodic action. Instead of threads continuously and periodically checking for data (busy-waiting), threads perform a single wait operation on their condition variable and remain inactive until an event occurs. When data becomes available, the producing thread sends a signal that triggers the waiting thread to wake up and check for data. This transforms continuous energy-wasting periodic polling into efficient event-triggered action, maintaining fast data detection while eliminating CPU cycle waste.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7962923B2System and method for generating a lock-free dual queue
Publication Date: 2011.06.14 LEVEL 3 COMMUNICATIONS LLC
  • US7962923B2 patent drawing
  • US7962923B2 patent drawing
  • US7962923B2 patent drawing

AI summary

A method of supporting condition synchronization for a shared data structure so as to provide concurrent access. A protocol is provided between a thread creating a request as part of a remove operation and a thread fulfilling a request as part of an add operation. The protocol provides for the thread making such a request to check the request_value field of the request node and then wait on its own condition variable. A requesting thread sets a requestor_id field of a request node with a value that identifies the thread. A fulfilling thread sets a request_value field of a request node with the address of the data node with the value, and then signals the requesting thread as identified by the requestor_id field. Upon receiving the signal, the requesting thread wakes up and retrieves the value from the data node pointed to it by the request_value field of the request node. If a wait times out, the requesting thread attempts to signal that the wait timed out by performing a CAS operation on the request_value field to modify it from zero to non-zero. If the CAS operation succeeds, the request timed out and the remove operation return failure. If the CAS operation fails, the request was fulfilled since the fulfilling thread set the request_value field with the address of the data node.