Lock-Free RAID Stripe Isolation for NVMe Multi-Queue Performance

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Solution Overview

Problem

Conventional RAID solutions fail to optimize performance with the increased capabilities of NVME drives due to lock acquisition and contention, leading to bottlenecks in storage software design, especially in multi-queue architectures.

Innovation Solution

Implementing a lock-free RAID system by isolating RAID stripes to a single CPU core affinity, allowing requests to be efficiently routed to the CPU that owns the data, eliminating the need for locks and enabling asynchronous, scalable operations across multiple CPU cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional RAID solutions are used with multi-queue hardware, then data redundancy and storage reliability are maintained, but lock acquisition and contention create performance bottlenecks

Engineering Contradiction:

Improvedata redundancyVSAvoidstorage performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the storage system by assigning each CPU core its own dedicated RAID stripe sets, creating isolated processing domains. This segmentation eliminates the need for locks between cores while maintaining data redundancy through distributed RAID operations across multiple cores and stripe sets.

Inventive Principle:

Principle #1Segmentation

2Stability of the object's composition

If locks are used to protect shared data structures in RAID operations, then data consistency is maintained, but synchronization overhead reduces system throughput

Engineering Contradiction:

Improvedata consistencyVSAvoidsystem throughput

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

Each CPU core is assigned specific RAID stripe sets with exclusive access rights, creating local ownership domains. This local quality approach ensures data consistency within each core's domain without requiring global synchronization, thereby eliminating lock overhead while maintaining integrity.

Inventive Principle:

Principle #3Local quality

3Reliability

If software intensive algorithms are used for data compression and replication, then storage redundancy is achieved, but overall storage performance decreases

Engineering Contradiction:

Improvestorage redundancyVSAvoidstorage performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent replaces software-intensive RAID operations with hardware-accelerated NVME operations. By leveraging the parallel hardware interfaces and queues native to NVME controllers, RAID functions are executed in hardware rather than through software algorithms, dramatically improving performance while maintaining redundancy.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If conventional RAID designs are used, then compatibility with legacy drives is maintained, but parallel hardware interfaces in NVME devices cannot operate independently

Engineering Contradiction:

Improvelegacy compatibilityVSAvoidparallel interface performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces a new dimensional approach by mapping RAID stripe sets across multiple CPU cores and NVME queues simultaneously. This multi-dimensional assignment allows parallel NVME interfaces to operate independently across different cores and queues, breaking the single-threaded limitation of conventional RAID while maintaining legacy compatibility through standardized RAID level support.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10430336B2Lock-free raid implementation in multi-queue architecture

Publication Date: 2019.10.01 OVH US LLC

AI summary

Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.