Lock-Free Scalable Free List for Multi-Processor Systems

The patent divides the single global free list into multiple processor-specific free lists, where each processor has its own dedicated list. This segmentation localizes memory access to each processor's L1 cache, eliminating L2 cache misses caused by shared list access while maintaining efficient allocation and deallocation operations.

The patent combines multiple processor-specific free lists with a global free list into a unified hierarchical structure. When local lists are empty, processors can allocate from the global list, and excess items can be transferred to the global list for redistribution. This merging approach maintains the cache performance benefits of local lists while reducing overall system complexity through a fallback mechanism.

The patent uses threshold parameters to trigger automatic item transfers between free lists. When the number of items in a processor-specific list exceeds an upper threshold, excess items are transferred to the global list. When below a lower threshold, items are replenished from the global list. This parameter-based approach provides adaptive load balancing with simple, efficient operations that minimize processing overhead.