Lock Dependency Graph for Inter-Processor Interrupt Deadlocks
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Solution Overview
Problem
Existing deadlock detection methods in computer systems are limited in handling complex processor deadlocks, particularly in modeling and recording lock dependency graphs, as they fail to effectively capture restrictions on processor access such as disabling interrupts and inter-processor interrupts with synchronous waiting.
Innovation Solution
The method involves modeling and storing locking primitive information in a lock dependency graph for restrictions like disabling interrupts and sending inter-processor interrupts with synchronous waiting, treating these actions as locking primitives to predict and detect deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional locking primitives are used in lock dependency graph, then the graph can track traditional locks, but it cannot detect deadlocks involving interrupt disabling or inter-processor interrupts
Solution Approach 1:
The patent extends the lock dependency graph to handle multiple types of processor access restrictions uniformly. By treating interrupt disabling and inter-processor interrupts as locking primitives equivalent to traditional locks, the system achieves universal deadlock detection across diverse synchronization mechanisms. The graph structure remains the same, but now accommodates conventional locks, interrupt disable regions, and IPI operations through a unified representation framework.
Solution Approach 2:
The patent introduces new parameters and attributes to the lock dependency graph to represent non-traditional locking behaviors. Specifically, it adds parameters to track interrupt state (enabled/disabled) and IPI synchronization status, transforming the graph's capability to model these operations. This parameter extension allows the existing graph structure to detect deadlocks involving processor access restrictions without fundamental architectural changes.
2Reliability
If the lock dependency graph is extended to model interrupt disabling and IPI operations, then deadlock detection improves, but the complexity of the graph increases
Solution Approach 1:
The patent segments the representation of processor access restrictions into distinct locking primitive types within the lock dependency graph. Each type (conventional lock, interrupt disable, IPI operation) is represented as a separate node or edge type with specific attributes. This segmentation allows the graph to handle complexity through structured classification rather than monolithic representation, making the system manageable while maintaining comprehensive deadlock detection.
Solution Approach 2:
The patent introduces an intermediary layer of abstraction between the hardware-level processor operations and the software-level deadlock detection. By defining a standardized interface that maps interrupt disabling and IPI operations to locking primitive concepts, the system mediates between these different operational domains. This intermediary representation simplifies the graph structure by providing a common language for diverse synchronization mechanisms.
Data Source
AI summary
Creating, maintaining and using a lock dependency graph in a way that includes the following steps: (i) acquiring a first restriction on processor access in a multi-processor computer system; (ii) modeling the first restriction as first locking primitive information; and (iii) storing data corresponding to the first locking primitive information in a lock dependency graph. The first restriction on processor access is one of the following two types: (i) disabling the interrupts on a given processor; and/or (ii) sending inter-processor interrupts with synchronous waiting from one processor to another (including itself).