Multi-Channel Lock-In Amplifier Synchronization for Accurate Aggregation

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Solution Overview

Problem

Conventional lock-in amplifiers face challenges in generating accurate aggregated measurement values due to timing differences between channels, leading to degraded quality, especially when measuring time-varying signals or objects with temperature dependencies.

Innovation Solution

A lock-in amplifier with multiple channels synchronized by a synchronization unit, generating synchronized output signals that are then aggregated by an aggregation module to produce accurate and stable results, even with time-varying currents or resistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple channels of lock-in amplifiers are used to measure aggregated aspects, then the ability to measure aggregated values is improved, but timing differences between channels cause degradation in measurement precision

Engineering Contradiction:
Improveability to measure aggregated valuesVSAvoidquality of aggregated value
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent combines multiple channels within a single lock-in amplifier device and synchronizes their operation through a shared clock signal. This merging approach allows aggregated measurements while eliminating timing differences between channels, as all channels are controlled by the same time reference. The synchronized channels work together to measure multiple aspects of the measured object simultaneously without the timing degradation that would occur with separate devices.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If conventional lock-in amplifiers measure signals with high resolution, then measurement precision is improved, but time shifts between channels distort results when measuring time-varying properties

Engineering Contradiction:
Improveresolution and accuracyVSAvoidaccuracy of aggregated value over time
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent uses a periodic clock signal to synchronize the operation of multiple channels at regular time intervals. This periodic synchronization ensures that all channels sample their respective signals at precisely aligned time points, eliminating time shifts between channels. The regular periodic action of the clock signal maintains consistent timing relationships throughout the measurement process, preventing distortion of time-varying properties while preserving high measurement precision.

Inventive Principle:
Principle #19Periodic action

3Productivity

If external aggregation of channel results is performed, then aggregated measurement values can be obtained, but timing differences between channels degrade the quality of aggregation

Engineering Contradiction:
Improvegeneration of aggregated valuesVSAvoidquality of aggregated value
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent introduces a clock signal as an intermediary that mediates the timing between multiple channels. This clock signal acts as a common reference that coordinates the operation of all channels, ensuring they produce their output signals at synchronized time points. The intermediary clock signal enables external aggregation of channel results to proceed with high quality, as the timing differences that would normally degrade aggregation are eliminated by this mediating time reference.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10404215B2Synchronized multiple channel lock-in amplifier
Publication Date: 2019.09.03 MOTZKAU HOLGER
  • US10404215B2 patent drawing
  • US10404215B2 patent drawing
  • US10404215B2 patent drawing

AI summary

The disclosure relates to a lock-in amplifier comprising a plurality of channels (CH.sub.1-CH.sub.N), wherein each channel of the plurality of channels (CH.sub.1-CH.sub.N) is configured to receive an input signal (S.sub.in1-S.sub.inN) and generate at least one output signal (S.sub.out1-S.sub.outN), a synchronization unit (110) configured to synchronize the generated output signals (S.sub.out1-S.sub.outN) of the plurality of channels (CH.sub.1-CH.sub.N), an aggregation module (150) configured to receive the generated output signals (S.sub.out1-S.sub.outN) and generate an aggregated signal (S.sub.agg) based on the generated output signals (S.sub.out1-S.sub.outN).