Lock Register Reset via Unlock Instruction Propagation
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Solution Overview
Problem
In multi-core processor systems, releasing a lock too early can cause other core processors to read stale data values, leading to performance degradation and power consumption issues due to stalling, as the lock release must wait for memory operations to become visible across the coherence domain.
Innovation Solution
A method where a core processor acquires a lock, performs processing functions, and sends an unlock instruction through a processing pipeline, allowing a lock reset signal to be provided once the instruction reaches the coherence domain, enabling the core processor to release the lock and perform additional functions or enter sleep mode before the unlock instruction propagates, thus reducing stall time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the core processor waits for the unlock instruction to reach the coherence domain before releasing the lock, then data integrity is maintained, but processor performance degrades due to stalling
Solution Approach 1:
The lock release is performed preliminarily (before the unlock instruction reaches the coherence domain) by decoupling the lock release action from the visibility confirmation. The processor releases the lock immediately after completing memory operations, while the unlock instruction continues propagating through the pipeline to the coherence domain separately. This preliminary action eliminates the stall while maintaining data integrity through the sequential consistency guarantee of the unlock instruction propagation.
2Reliability
If the core processor stalls to ensure memory operations become visible to other cores, then coherence is maintained, but power consumption increases
Solution Approach 1:
The processor performs the lock release action preliminarily without stalling, allowing immediate transition to sleep mode or other processing functions. The coherence requirement is satisfied by the subsequent propagation of the unlock instruction through the processing pipeline to the coherence domain, which occurs asynchronously without blocking the processor. This eliminates unnecessary power consumption during the lock release waiting period.
3Reliability
If the lock release is stalled to prevent other cores from reading stale data, then data consistency is ensured, but processing throughput decreases
Solution Approach 1:
The lock release is executed as a preliminary action immediately after memory operations complete, without waiting for visibility confirmation. The data consistency is subsequently ensured by the unlock instruction propagating through the processing pipeline to the coherence domain, which asynchronously updates the visibility state to other cores. This decoupling eliminates the stall and maximizes processing throughput while maintaining sequential consistency.
Data Source
AI summary
An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.