Configurable Lock-Step Control for Automotive Hardware Accelerators
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Solution Overview
Problem
Existing automotive-grade hardware accelerators face challenges in efficiently processing complex data algorithms while meeting safety standards like ASIL-D, often requiring resource duplication that increases silicon area and power consumption.
Innovation Solution
A hardware accelerator device with configurable lock-step control units and interconnect networks that allow for dynamic operation modes, enabling fault detection and propagation without duplicating hardware resources, thus achieving ASIL-D safety levels without increasing silicon area or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware resources are duplicated according to conventional lock-step configuration to implement functional safety, then safety level (ASIL-D) is improved, but silicon area occupation increases
Solution Approach 1:
The patent merges the safety monitoring function into a shared resource that is time-multiplexed across processing circuits. Instead of dedicating separate monitoring hardware to each processing circuit, a single monitoring circuit is shared among multiple processing circuits through time-multiplexing, thereby reducing silicon area while maintaining ASIL-D safety levels.
Solution Approach 2:
The monitoring circuit operates dynamically by switching between different processing circuits in time-multiplexed fashion. The monitoring resource is not statically assigned but dynamically allocated to different processing circuits based on operational needs, allowing one monitoring circuit to serve multiple processing circuits without compromising safety.
2Reliability
If hardware resources are duplicated according to conventional lock-step configuration to implement functional safety, then safety level (ASIL-D) is improved, but power consumption increases
Solution Approach 1:
Multiple monitoring functions are merged into a single shared monitoring circuit that serves multiple processing circuits through time-multiplexing. This consolidation reduces the total number of active monitoring circuits simultaneously, thereby reducing overall power consumption while maintaining required safety levels.
Solution Approach 2:
The monitoring circuit dynamically activates and deactivates based on which processing circuit is currently being monitored. By switching the monitoring resource on and off for different processing circuits in sequence rather than keeping multiple monitoring circuits continuously active, power consumption is reduced while safety monitoring coverage is maintained.
3Speed
If complex data processing algorithms are processed in real-time, then processing speed is improved, but processing complexity increases
Solution Approach 1:
Complex data processing algorithms are segmented into multiple processing circuits that operate in parallel. Each processing circuit handles a specific portion of the algorithm (e.g., different stages of FFT or ANN processing), allowing real-time processing through parallel execution while managing individual circuit complexity.
Solution Approach 2:
The processing circuits are designed with universal, configurable functionality that can be dynamically configured to implement different algorithms or algorithm stages. This multi-functionality allows the same hardware structure to handle various complex algorithms (FFT, FIR, ANN) without requiring dedicated complex hardware for each algorithm, thereby reducing overall device complexity while maintaining real-time processing capability.
Data Source
AI summary
A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.