Locked-Loop Relocking Using Standby Spin-Up to Limit Drift

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Solution Overview

Problem

Traditional locked loops in electronic devices face challenges with power management, leading to increased latency and reduced accuracy when restarting from low-power modes due to drift caused by temperature and voltage changes, which affects the relocking duration and performance.

Innovation Solution

Implementing a system where internal power modes are decoupled from external power modes, allowing the locked loop to periodically 'spin up' and maintain a locked state during external standby modes, reducing relocking duration and increasing accuracy by constraining drift through internal run and pause modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the locked loop is completely powered down during external standby mode to save power, then power consumption is reduced, but relocking latency increases and accuracy decreases due to drift

Engineering Contradiction:
Improvepower consumptionVSAvoidrelocking latency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The locked loop performs preliminary actions by spinning up the loop to lock during external standby mode before full operation is needed. This keeps the loop warm and reduces drift, so when normal operation resumes, the relocking latency is minimized while still achieving significant power savings compared to keeping the loop fully active.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If the locked loop is completely powered down during external standby mode to save power, then power consumption is reduced, but accuracy decreases due to temperature and voltage drift

Engineering Contradiction:
Improvepower consumptionVSAvoidfrequency accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The system performs preliminary locking actions during external standby mode to maintain frequency accuracy. By spinning up the loop to lock before normal operation, the loop remains warm and stable, minimizing temperature and voltage drift effects while still achieving substantial power reduction compared to continuous operation.

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If the locked loop continuously runs to maintain accuracy and minimize latency, then relocking latency is reduced and accuracy is maintained, but power consumption increases

Engineering Contradiction:
Improverelocking latencyVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

Instead of continuous operation, the locked loop uses periodic action by spinning up the loop to lock at intervals during external standby mode. This periodic maintenance locking achieves the dual benefit of keeping the loop warm (reducing relocking latency and maintaining accuracy) while significantly reducing power consumption compared to continuous operation.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10374651B1Systems and methods of relocking for locked loops
Publication Date: 2019.08.06 QUALCOMM INC
  • US10374651B1 patent drawing
  • US10374651B1 patent drawing
  • US10374651B1 patent drawing

AI summary

An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode.