Lockless Buffer Ring for Low-Latency Pub-Sub Messaging

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Solution Overview

Problem

Existing publish-subscribe systems face challenges in providing low-latency, reliable, and scalable data access in robotic applications like autonomous vehicles, particularly due to limitations in buffer ring architectures that lead to increased latency and performance issues as the number of processing modules and data exchanged between them grows.

Innovation Solution

A lockless buffer ring system is implemented using a shared memory with a global header and synchronization data storage region, allowing publishers and subscribers to efficiently write and read messages without blocking, using a seqlock counter and futex system calls for synchronization, ensuring accurate message transfer and handling of concurrent operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a buffer ring architecture is used to store messages in shared memory, then data access is simplified and memory usage is efficient, but latency increases and performance degrades as the number of processing modules and data exchanged grows

Engineering Contradiction:
Improvedata access efficiencyVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The buffer ring is divided into multiple fixed-size buffers arranged sequentially in shared memory, with each buffer capable of storing individual messages. This segmentation allows multiple publishers and subscribers to access different buffers concurrently without blocking each other, reducing latency while maintaining efficient memory usage

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A global header containing a seqlock counter is introduced as an intermediary mechanism to coordinate access between multiple publishers and subscribers. The counter provides synchronization information without requiring traditional locking, enabling concurrent operations while maintaining data integrity and reducing latency

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If traditional locking mechanisms are used to ensure data consistency in shared memory, then reliability is improved, but latency increases and throughput decreases due to blocking operations

Engineering Contradiction:
Improvedata consistencyVSAvoidaccess latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Traditional mechanical locking mechanisms are replaced with a software-based seqlock counter system. The counter provides synchronization through atomic read-modify-write operations and memory ordering guarantees, eliminating blocking while ensuring data consistency. Publishers and subscribers can proceed without acquiring locks, significantly reducing access latency while maintaining reliability through the counter's synchronization semantics

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Quantity of substance

If the buffer ring size is increased to accommodate more messages, then the system can handle higher data volumes, but memory usage increases and access latency may worsen due to longer search paths

Engineering Contradiction:
Improvemessage capacityVSAvoidmessage access time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The buffer ring is segmented into multiple fixed-size buffers that can be accessed independently. This allows the system to handle higher message volumes by distributing messages across multiple buffers while maintaining constant access time, as each buffer remains a fixed, small size that can be accessed in constant time without traversing a longer structure

Inventive Principle:
Principle #1Segmentation

4Productivity

If lockless operations are implemented to reduce latency, then throughput is improved, but ensuring data consistency and handling concurrent operations becomes more complex

Engineering Contradiction:
ImprovethroughputVSAvoidsynchronization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A global header containing a seqlock counter serves as an intermediary synchronization mechanism that simplifies lockless operations. The counter provides a single point of coordination that publishers and subscribers can atomically read and update without complex locking protocols. This intermediary structure reduces synchronization complexity while enabling high-throughput lockless operations through atomic counter operations and memory ordering

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11429290B2Methods and systems for providing a lockless access to a shared memory region in a publish and subscribe system
Publication Date: 2022.08.30 FORD GLOBAL TECH LLC
  • US11429290B2 patent drawing
  • US11429290B2 patent drawing
  • US11429290B2 patent drawing

AI summary

Systems and methods for providing lockless access to a buffer ring are disclosed. The systems include a shared memory comprising the buffer ring. The buffer ring includes a plurality of sequentially arranged fixed size buffers configured to store messages, and a global header comprising a counter and a lock. The systems further include a publisher configured to write a plurality of messages to the plurality of fixed sized buffers in the buffer ring, and a subscriber configured to read one or more of the plurality of messages written by the publisher. The counter provides information relating to a fixed size buffer in the buffer ring to which the publisher will next write a message.