Lockless FIFO Buffer Data Exchange Between Processing Units
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Solution Overview
Problem
Distributed computing systems face inefficiencies due to the use of ring buffers, which require locking and coordination between processing units, leading to resource loss and computational underutilization, and existing solutions are resource-intensive with dedicated channels between each pair of communicating units.
Innovation Solution
The implementation of two unidirectional atomically accessed FIFO buffers and a commonly accessible memory device allows for lockless data exchange between processing units, enabling independent operation without the need for resource locking or coordination, using buffer identifiers and interrupt signals for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If locking mechanisms are used to coordinate data exchange between processing units, then data consistency is improved, but system performance deteriorates due to resource loss and computational underutilization
Solution Approach 1:
The patent extracts the coordination function from the data exchange mechanism by introducing separate control registers (head pointer, tail pointer, length) that are independently accessible by sending and receiving processing units. This allows data consistency to be maintained through atomic operations on these registers rather than through locking mechanisms, thereby eliminating the performance penalty associated with locks while preserving data integrity.
Solution Approach 2:
The patent introduces an intermediary data structure (the ring buffer with separate control registers) that mediates between sending and receiving processing units. This intermediary provides a shared memory region with atomic access controls, enabling coordinated data exchange without requiring direct locking interactions between the processing units, thus maintaining both consistency and performance.
2Reliability
If dedicated communication channels are established between each pair of processing units, then communication reliability is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent implements a universal communication mechanism where a single shared memory region (ring buffer) serves all processing units for data exchange. Instead of requiring dedicated channels between each pair of units, any processing unit can send or receive data through this common infrastructure, reducing system complexity while maintaining communication reliability through atomic operations and control registers.
Solution Approach 2:
The patent merges multiple dedicated communication channels into a single shared memory region that is accessible by all processing units. By combining the communication infrastructure into one unified resource with atomic access controls, the system achieves the reliability of dedicated channels without the complexity of implementing separate channels for each processor pair.
Data Source
AI summary
Some examples comprise a memory device including a memory region accessible by a receiving processing unit and a plurality of sending processing units, the memory region including a set of memory buffers identified by a set of buffer identifiers; a first FIFO buffer for communicating a first buffer identifier from the receiving processing unit to any of the sending processing units, the first buffer identifier corresponding to a memory buffer available for use by the any one sending processing unit in sending data to the receiving processing unit; and a second FIFO buffer for communicating a second buffer identifier to the receiving processing unit from any of the sending processing units, the second buffer identifier corresponding to a memory buffer containing data being sent to the receiving unit.