Lockless Shared Memory for Multi-Core Network CPU Performance
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Solution Overview
Problem
In symmetric multiprocessing (SMP) architectures, the use of a global atomic counter and shared memory locking mechanisms can lead to performance degradation due to indeterministic behaviors and increased CPU time usage, especially when multiple CPU cores access and update network packet counters simultaneously.
Innovation Solution
Implementing a lockless shared memory design where each CPU core maintains its own non-atomic counter, eliminating the need for a global atomic counter and locking mechanism, allowing for direct read and write access by CPU cores without data integrity issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global atomic counter is used across multiple networking CPUs, then data integrity is maintained, but performance is degraded due to expensive atomic operations
Solution Approach 1:
The patent divides the single global atomic counter into multiple per-CPU non-atomic counters. Each networking CPU maintains its own counter in lockless shared memory, eliminating the need for atomic operations while maintaining data integrity through individual tracking of packet counts per CPU core.
Solution Approach 2:
The patent introduces a dedicated CPU as an intermediary that periodically aggregates the per-CPU non-atomic counters into a global counter. This mediator approach allows individual CPUs to use fast non-atomic operations while still maintaining an accurate global view through the dedicated aggregation CPU.
2Reliability
If locking mechanisms are implemented on shared memory, then data access safety is ensured, but performance is degraded due to CPU time usage for locking operations
Solution Approach 1:
The patent extracts the locking mechanism entirely from the shared memory access path. By using lockless shared memory design, the system removes the harmful locking operations that were causing performance degradation, while maintaining data safety through the per-CPU counter architecture and dedicated aggregation CPU.
Solution Approach 2:
Each CPU core independently maintains its own counter without requiring locks or coordination with other CPUs. The per-CPU counters are updated in lockless shared memory without interference from other CPUs, allowing each core to serve itself without external control.
3Productivity
If multiple CPUs access the same data structure simultaneously, then resource utilization is maximized, but indeterministic behaviors occur including incorrect reading of data values
Solution Approach 1:
The patent segments the shared data structure into separate per-CPU counters, where each CPU has its own dedicated counter in lockless shared memory. This segmentation eliminates race conditions and indeterministic behaviors by ensuring that each CPU reads and writes its own counter without interference from other CPUs.
Solution Approach 2:
The patent assigns different properties to different parts of the counter system - each per-CPU counter is local to its owning CPU and can be accessed without locks, while the global counter is maintained separately by the dedicated CPU. This local quality approach allows simultaneous access by multiple CPUs without data corruption.
Data Source
AI summary
The present disclosure discloses a method and network device for achieving enhanced performance with multiple CPU cores in a network device having a symmetric multiprocessing architecture. The disclosed method allows for storing, by each central processing unit (CPU) core, a non-atomic data structure, which is specific to each networking CPU core, in a memory shared by the plurality of CPU cores. Also, the memory is not associated with any locking mechanism. In response to a data packet is received by a particular CPU core, the disclosed system will update a value of the non-atomic data structure corresponding to the particular CPU core. The data structure may be a counter or a fragment table. Further, a dedicated CPU core is allocated to process only data packets received from other CPU cores, and is responsible for dynamically responding to queries receives from a control plane process.