Lockless Stateful NAT in Multicore Systems
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Solution Overview
Problem
Stateful network address translation in multicore computing systems faces scalability issues due to the need for mutual exclusion locks, which limit performance by causing interlocking and cache thrashing among cores.
Innovation Solution
The approach binds packet flows to a single processing core using a local cache for stateful information and selects a new port from pre-computed hash/port pairs stored in a mapping table, eliminating the need for mutual exclusion locks by ensuring bidirectional packet flows are assigned to the same core through symmetric translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mutual exclusion locks are used to ensure thread-safe access to state data in stateful NAT, then data consistency is maintained, but system performance and scalability deteriorate due to interlocking and cache thrashing between multiple cores
Solution Approach 1:
The patent divides the shared state data into per-core state data structures, where each processing core has its own dedicated state data. This segmentation eliminates the need for mutual exclusion locks because each core operates on its own data without interfering with other cores. The state data is partitioned based on core affinity, allowing parallel processing while maintaining data consistency without interlocking.
2Productivity
If packets of the same bidirectional flow are handled by threads on different processing cores, then load balancing is improved, but cache thrashing increases due to frequent access to shared state data
Solution Approach 1:
The patent implements local cache storage for state data at each processing core, making the most frequently accessed state information locally available. This local cache reduces the need for remote memory accesses and minimizes cache thrashing. The state data is organized with local cache structures that are specific to each core's processing needs, improving energy efficiency while maintaining load balancing across cores.
3Device complexity
If a shared state data structure is used across all processing cores, then implementation simplicity is maintained, but scalability is limited due to lock contention
Solution Approach 1:
The patent segments the shared state data structure into per-core instances, where each processing core has its own state data structure. This segmentation enables scalability to multiple cores by eliminating lock contention, while the overall architecture remains relatively simple and follows a straightforward per-core processing model. The segmentation is transparent to the packet processing logic, maintaining implementation simplicity.
Data Source
AI summary
Examples include a computing system having a plurality of processing cores and a memory coupled to the plurality of processing cores. The memory has instructions stored thereon that, in response to execution by a selected one of the plurality of processing cores, cause the following actions. The selected processing core to receive a packet and get an original tuple from the packet. When no state information for a packet flow of the packet exists in a state table, select a new network address as a new source address for the packet, get a reverse tuple for a reverse direction, select a port for the packet from an entry in a mapping table based on a hash procedure using the reverse tuple, and save the new network address and selected port. Translate the packet's network address and port and transmit the packet.