Lockless Threading Model for Storage Target I/O Performance

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Solution Overview

Problem

In storage area networks, the synchronization points established in the data path between initiators and targets can significantly affect input/output performance, especially when multiple sessions access multiple logical units in parallel, due to connection-specific and LUN-specific processing contexts.

Innovation Solution

A novel threading model that splits transport protocols and SCSI core protocols into separate threads with a lockless queue design, allowing independent scheduling of CPU resources for transport protocol threads and SCSI core threads, maximizing cache locality and eliminating lock contention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the entire I/O path is executed in a thread context of the transport protocol layer, then connection-specific processing is maintained, but synchronization points are established at both LUN level and connection level, affecting overall I/O performance

Engineering Contradiction:
Improveconnection-specific processing integrityVSAvoidoverall I/O performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the I/O processing path into two distinct thread contexts: transport protocol layer threads (handling connection-specific operations) and SCSI core layer threads (handling LUN-specific operations). This segmentation allows each layer to process I/O commands independently without establishing synchronization points between them, thereby maintaining connection-specific processing integrity while eliminating the performance bottleneck caused by multi-level synchronization.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple sessions access multiple LUNs in parallel, then I/O throughput is increased, but synchronization bottlenecks are amplified due to multiple synchronization points in the data path

Engineering Contradiction:
ImproveI/O throughputVSAvoidsynchronization delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the processing architecture into separate transport threads and data path threads that operate in parallel without synchronization barriers. Transport threads handle connection-level operations while data path threads handle LUN-level operations independently, allowing multiple sessions to access multiple LUNs simultaneously without encountering synchronization bottlenecks, thus maintaining high I/O throughput without time loss.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces lockless queues as intermediary data structures between transport threads and data path threads. These queues enable asynchronous communication and data transfer between the two thread types without requiring locks or synchronization mechanisms, allowing parallel access to multiple LUNs while eliminating synchronization delays.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If lockless queue design is implemented with separate thread groups, then lock contention is eliminated and cache locality is maximized, but system complexity increases due to multiple CPU groups and thread management

Engineering Contradiction:
ImproveI/O performanceVSAvoidthread management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the CPU resources into two distinct groups: first CPU group dedicated to transport threads and second CPU group dedicated to data path threads. This segmentation enables lockless queue operations where each CPU group operates independently, eliminating lock contention and maximizing cache locality. Although this increases hardware resource allocation, it maintains I/O performance while managing complexity through clear functional separation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10146439B2System and method for high performance lockless scalable target
Publication Date: 2018.12.04 SAMSUNG ELECTRONICS CO LTD
  • US10146439B2 patent drawing
  • US10146439B2 patent drawing
  • US10146439B2 patent drawing

AI summary

A method for accessing data stored in a target of a data storage system includes: running a plurality of transport threads on a first group of CPUs, wherein each of the plurality of transport threads comprises a command receiver path and a command transmitter path; running a plurality of data path threads on a second group of CPUs, wherein each of the plurality of data path threads comprises a command issue path and a command completion path; posting an I/O command to an I/O command issue queue using the command receive path of a transport thread, and processing the I/O command using the command issue path of a data path thread; and posting an I/O completion notification to an I/O completion queue using the command completion path of the data path thread, and processing the I/O completion notification using the command transmitter path of the transport thread.