Lockstep Processor Auto-Recovery via Pending Instruction Mismatch Detection
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Solution Overview
Problem
Existing lockstep processing systems in dual-core processors require system resets and interrupt service, leading to service interruptions and increased design complexity when detecting errors, and existing recovery methods reduce processing throughput or require software modifications.
Innovation Solution
A system and method that includes a lockstep monitor with checkpoint and auto-recovery circuitry to detect mismatches in pending instructions and perform auto-recovery operations, preventing processors from executing erroneous instructions without requiring a system reset or software changes, by generating and transmitting flush and re-execute interrupts to re-execute pipelined instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If system reset is performed to recover from detected error, then error recovery is achieved, but service interruption occurs and design complexity increases
Solution Approach 1:
The patent performs preliminary actions by detecting and correcting errors in the pending instruction stage before execution. The lockstep monitor compares pending instructions from both processors and identifies mismatches early in the pipeline, allowing correction before the erroneous instruction affects system state. This preliminary detection and correction eliminates the need for system resets while maintaining service continuity.
Solution Approach 2:
The patent introduces an intermediary mechanism (lockstep monitor with auto-recovery circuitry) that mediates between the dual processors. This intermediary detects mismatches in pending instructions and triggers selective re-execution of only the affected pipeline stages, rather than resetting the entire system. The intermediary enables localized error handling that maintains overall system operation.
2Reliability
If software checkpoint and recovery is used, then error recovery is achieved, but processing throughput is reduced
Solution Approach 1:
The patent performs preliminary error detection and correction in the pending instruction stage, before execution. By identifying mismatches early in the pipeline and correcting them through selective re-execution of only affected stages, the system avoids the need to save and restore software checkpoints. This eliminates the overhead associated with checkpointing while maintaining error recovery capability.
Solution Approach 2:
The patent discards the erroneous pending instruction and recovers by re-executing only the affected pipeline stages. Instead of saving complete software state for potential recovery, the system simply re-executes the specific instruction that caused the mismatch. This selective re-execution approach recovers from errors without the throughput penalty of full checkpointing.
3Measurement precision
If error detection is performed at system bus, then error detection is achieved, but recovery requires system reset
Solution Approach 1:
The patent segments the error detection and recovery process into fine-grained pipeline stages. Instead of detecting errors only at the system bus level, the lockstep monitor compares pending instructions at intermediate pipeline stages. This segmentation allows detection of mismatches earlier in the execution flow, enabling recovery from individual instruction errors without affecting the entire system or requiring global resets.
Solution Approach 2:
The patent performs preliminary error detection at the pending instruction stage, before the instruction is executed and before it reaches the system bus. By detecting mismatches in advance and correcting them through selective re-execution, the system maintains service continuity without requiring interrupts or resets that would occur with later-stage detection.
Data Source
AI summary
A system and method for monitoring processors operating in lockstep to detect mismatches in pending pipelined instructions being executed by the processors. A lockstep monitor implemented in hardware is provided to detect the mismatches in the pending pipelined instructions executing on the lockstep processors and to initiate an auto-recovery operation at the processors if a mismatch is detected.