Lockstep Comparator Self-Test for Fast Fault Isolation
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Solution Overview
Problem
Existing lockstep testing implementations are intrusive, slow, and unable to isolate fault conditions in lockstep hardware, requiring offline testing and lacking the ability to provide comprehensive debug information for improving lockstep hardware operation.
Innovation Solution
The implementation of lockstep comparators that enable online test sequencing and diagnostic data output, allowing for fast diagnostic execution and comprehensive fault condition analysis without taking the lockstep hardware offline, using redundant hardware and comparator logic to compare outputs from multiple cores and generate detailed debug data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing lockstep testing implementations are used, then fault detection capability is provided, but test time is excessively long (thousands of cycles) and the system must be taken offline
Solution Approach 1:
The testing function is segmented into multiple independent comparators (first comparator, second comparator) that can operate simultaneously in parallel. This allows the test to be divided into multiple concurrent test sequences rather than executing a single long sequential test, thereby reducing total test time while maintaining comprehensive fault detection capability
Solution Approach 2:
The comparators are configured to perform self-tests and diagnostic operations preliminarily during normal lockstep operation. Test patterns are applied and comparisons are made before actual faults occur, enabling early detection without requiring system shutdown. The diagnostic data is collected and analyzed in advance to identify potential issues
2Reliability
If existing lockstep testing implementations are used, then fault detection is possible, but comprehensive debug information cannot be obtained
Solution Approach 1:
The comparators provide continuous feedback through diagnostic data outputs that indicate the status of lockstep operation and any detected faults. The diagnostic data includes detailed information about comparison results, fault conditions, and system state, enabling comprehensive analysis and debugging without losing critical information about system behavior
Solution Approach 2:
The comparators act as intermediary components between the lockstep cores and the diagnostic system. They capture and translate internal comparator states into external diagnostic data that can be analyzed, preserving detailed information about fault conditions while enabling external observation and debugging
3Productivity
If existing lockstep testing implementations are used, then testing can be performed, but the system must be taken offline requiring intrusive intervention
Solution Approach 1:
The lockstep system continues to perform its useful computation function continuously while the comparators simultaneously perform testing operations. The testing action does not interrupt or pause the primary computational function, allowing both operations to proceed without interruption and maintaining system availability throughout the testing process
Solution Approach 2:
The comparators perform self-tests and self-diagnosis without requiring external intervention or system shutdown. The testing mechanism is self-contained and autonomous, capable of initiating and completing test sequences independently while the lockstep system continues normal operation, eliminating the need for intrusive offline testing
Data Source
AI summary
Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.