Lockstep Core Error Classification for Minimal Downtime
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Solution Overview
Problem
Current data processing systems with lockstep operation lack efficient mechanisms to differentiate between soft and hard errors in real-time, leading to potential system downtime and reduced reliability in safety-critical applications.
Innovation Solution
A data processing system that compares output signals from two processing cores, enters a safe mode upon detecting a fault, and performs built-in self-tests (MBIST and LBIST) to determine if the fault is a soft or hard error, isolating the faulty core and allowing the non-faulty core to continue operation in a degraded mode or resetting the core domain as necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lockstep operation with error detection is implemented, then system reliability is improved, but system downtime increases due to inability to quickly differentiate error types
Solution Approach 1:
The patent implements preliminary classification of errors into soft errors and hard errors through specific detection mechanisms (parity error detection for soft errors, address mismatch detection for hard errors). This preliminary action enables the system to pre-determine the appropriate response strategy before full system shutdown, thereby reducing downtime while maintaining reliability.
Solution Approach 2:
The patent applies different error handling strategies to different error types locally. Soft errors trigger a safe mode with continued operation using alternative resources, while hard errors trigger a full shutdown. This localized quality-based response optimizes the balance between reliability and downtime by matching the response severity to the error severity.
2Reliability
If comprehensive error detection and classification mechanisms are added, then system safety is improved, but device complexity increases
Solution Approach 1:
The patent segments error detection into distinct functional modules: parity error detection unit for soft errors, address comparison unit for hard errors, and separate handling pathways. This segmentation improves safety through comprehensive coverage while managing complexity through modular design, where each module has a specific, simple function.
Solution Approach 2:
The patent uses parameter changes in the form of status flags and error codes to represent different error conditions. By changing the state of detection parameters (parity check results, address match flags), the system achieves comprehensive error classification without adding complex structural elements, thereby improving safety while controlling complexity.
3Reliability
If the system shuts down completely upon error detection, then system safety is improved, but productivity decreases due to loss of operational capacity
Solution Approach 1:
The patent implements dynamic error response where the system behavior adapts based on the error type detected. For soft errors, the system transitions to a safe mode that maintains partial operation (dynamic adaptation). For hard errors, the system performs a complete shutdown. This dynamic approach optimizes the balance between safety and productivity by matching the response intensity to the actual risk level.
Solution Approach 2:
The patent performs preliminary error classification before determining the shutdown strategy. By pre-identifying whether an error is soft or hard through dedicated detection circuits, the system can pre-determine the appropriate response level, avoiding unnecessary complete shutdowns for recoverable errors and thus maintaining productivity while ensuring safety.
Data Source
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AI summary
A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.