Delayed Lockstep CPU Switching for Fault-Tolerant Semiconductors
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Solution Overview
Problem
Existing semiconductor devices that employ a lockstep technique to enhance reliability fail to continue operations in the event of hardware failure within a CPU core, thereby limiting the improvement in reliability.
Innovation Solution
A semiconductor device configuration that includes a main device and a sub device operating in a delayed lockstep mode, with a delay circuit to delay the output of the main device and a switching circuit to switch operations from the main device to the sub device based on failure information, ensuring continuous operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lockstep technique is used to enhance reliability, then reliability is improved, but the device cannot continue operations in the event of hardware failure
Solution Approach 1:
The patent applies preliminary action by preparing a standby CPU core in advance that can take over operations if the main CPU core fails. The standby core is pre-configured and ready to execute, ensuring that operation continuation is possible without waiting for recovery or reconfiguration after failure occurs.
Solution Approach 2:
The patent changes the operational state parameter of the CPU cores by switching from a single-active configuration to a standby-active configuration upon failure detection. This parameter change enables the system to adapt its operational mode to maintain reliability and continuity despite hardware failure.
2Speed
If delay circuits are used to alleviate timing constraints, then timing constraints are improved, but device complexity increases
Solution Approach 1:
The patent merges the delay circuit functionality into the clock signal distribution system by using a single delay circuit that delays the clock signal to both the main and standby CPU cores. This combined approach achieves timing alignment without requiring separate delay circuits for each core, thereby reducing overall device complexity.
Data Source
AI summary
A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.