Lockstep CPU Core Availability via State Buffer Reload
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Solution Overview
Problem
Conventional embedded safety-relevant systems face significant downtime due to CPU core errors, which are addressed by resetting the entire system, resulting in prolonged unavailability for processing, and more complex systems increase availability at the cost of area, power, and cost.
Innovation Solution
A lockstep system comprising a main CPU core, a checker CPU core, a state buffer, and a comparator that compares outputs and generates control signals to reload a known good CPU state upon error detection, allowing for selective core reinitialization rather than full system reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire system is placed into a reset state upon CPU core error detection, then error correction is achieved, but system availability decreases significantly
Solution Approach 1:
The patent segments the reset operation from the full system to only the CPU core that detected the error. When a CPU core error is detected through lockstep comparison, only the affected CPU core is reset and reinitialized, while the rest of the system including other CPU cores, memory, and I/O devices continue operating without interruption. This segmentation resolves the contradiction by maintaining system availability while still achieving error correction.
2Loss of time
If three or more CPU cores with majority voting are used, then CPU core availability increases, but area, power consumption and cost increase
Solution Approach 1:
The patent implements preliminary action by maintaining a saved state of the CPU core in a buffer before error detection occurs. When an error is detected through lockstep comparison, the system can quickly restore the CPU core to its previous good state without needing to re-execute instructions or wait for complex voting procedures. This preliminary state saving resolves the contradiction by achieving high availability with the existing two-core lockstep system, avoiding the need for three or more cores.
Data Source
AI summary
A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core.