Lockstep Debug Circuitry for Semiconductor Core Efficiency
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Solution Overview
Problem
Existing debugging methods for microcontrollers in control devices, such as those used in vehicles, are inefficient and do not effectively utilize lockstep methods to facilitate debugging operations, leading to difficulties in detecting failures and acquiring internal information during program development.
Innovation Solution
A debugging system employing a lockstep dual-core configuration with a main processor core and a redundant lockstep core, where the debugging control circuitry allows for independent execution control and breakpoint settings, enabling efficient debugging by ensuring the lockstep core's internal information matches the main core's information while maintaining the main core's execution state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the lockstep method is used for debugging, then the reliability of failure detection is improved, but the productivity of debugging operations deteriorates due to the need to stop main core execution
Solution Approach 1:
The system separates the debugging function from the main execution function by using two distinct processor cores: the main core for normal program execution and the lockstep core for debugging operations. This segmentation allows each core to perform its specialized function independently, resolving the contradiction between maintaining execution reliability and preserving debugging productivity.
Solution Approach 2:
The lockstep core serves as a copy of the main core, replicating its instructional unit and operational characteristics. This copying enables the lockstep core to execute debugged programs while the main core continues normal operations, allowing failure detection without stopping productivity-critical execution.
2Measurement precision
If the main core execution is stopped for debugging, then the measurement precision of internal information is improved, but the loss of time increases due to execution interruptions
Solution Approach 1:
By creating a lockstep core that copies the main core's functionality, the system can capture and analyze internal information (register values, instruction states) from the lockstep core without interrupting the main core's execution. This copying mechanism provides measurement precision while avoiding time loss.
Solution Approach 2:
The lockstep core acts as an intermediary that facilitates debugging operations. It receives the same program instructions as the main core but allows external debugging access, serving as a mediator between the running system and the debugging tools without requiring main core interruption.
3Reliability
If the error detection function is continuously active, then the reliability of failure detection is improved, but the productivity during debugging deteriorates due to unnecessary error signals
Solution Approach 1:
The error detection function is applied locally and selectively: the coincidence determination circuit compares outputs only when needed for validation, and the error detection circuit is configured to distinguish between genuine errors and expected differences during debugging. This localized application maintains reliability while preventing productivity degradation from false alarms.
Solution Approach 2:
The system dynamically adjusts error detection behavior based on operational mode. During normal operation, error detection is active and strict. During debugging operations, the system dynamically modifies the error detection criteria to accommodate the special needs of debugging, preventing unnecessary interruptions while maintaining safety.
Data Source
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AI summary
Debugging a program in an apparatus using a lockstep method are more efficiently performed. A semiconductor apparatus includes a first processor core, a second processor core, a first debug circuit, a second debug circuit, and an error control circuit capable of outputting an error signal for stopping execution of a program by the first processor core and the second processor core. The second debug circuit performs setting regarding debugging different from that of the first processor core with respect to the second processor core. Even if a first processing result of the first processor core and a second processing result of the second processor core do not coincide with each other, the error control circuit invalidates the output of the error signal when the first processor core executes the program and the second processor core stops execution of the program based on the setting regarding debugging.