Lockstep ECC Hardware for Cross-Path Fault Detection
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Solution Overview
Problem
Conventional Error Correction Circuits (ECC) in memory systems face transient or permanent errors in their logic hardware, leading to incorrect data writing or incorrect flagging of memory read data, requiring significant additional logic for detection and correction due to independent operation of write and read path circuitry.
Innovation Solution
Implementing lockstep ECC circuit hardware with cross-coupled connections between write and read path circuitry, allowing the reuse of ECC generation logic for error detection and correction, reducing the overall ECC logic requirement and semiconductor chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross-coupled connections are added between write and read path circuitry to enable error detection, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The ECC generation logic in the write path is made multi-functional by adding cross-coupled connections that allow it to generate ECC for both write operations and error detection during read operations. Similarly, the read path ECC logic can function as both error checking and error detection, eliminating the need for separate dedicated error detection logic units.
Solution Approach 2:
The patent merges the error detection function with the existing ECC generation and checking logic by establishing cross-coupled connections between write and read paths. This combines multiple functions (ECC generation, ECC checking, and error detection) into the existing circuitry rather than adding separate dedicated error detection units.
2Reliability
If additional ECC generation logic is added on both sides to detect transient/permanent errors, then error detection capability is improved, but chip area increases
Solution Approach 1:
Existing ECC generation logic units are made universal to perform both traditional ECC generation for data protection and additional error detection functions. The write path ECC logic can detect errors in read path operations, and vice versa, eliminating the need for separate dedicated error detection logic units and reducing overall chip area.
Solution Approach 2:
Each ECC logic unit serves itself and the other path by generating ECC that can be used for both protecting its own path and detecting errors in the cross-coupled path. This self-service capability reduces the need for external or additional dedicated error detection resources.
3Device complexity
If write path and read path circuitry operate independently without cross coupling, then device complexity is reduced, but error detection capability deteriorates
Solution Approach 1:
Cross-coupled connections establish feedback loops where the write path ECC logic receives input from or compares with read path operations, and vice versa. This feedback mechanism enables error detection by allowing each path to verify the correctness of operations in the other path, improving reliability while maintaining manageable complexity.
Data Source
AI summary
Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.