Lockstep Microcomputer Bus Contention and Reliability
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Solution Overview
Problem
Existing microcomputers with lockstep systems face challenges in using general-purpose CPUs, as they require dedicated paths for each CPU, leading to contention on the system bus and reduced processing efficiency when multiple CPUs access the same address.
Innovation Solution
A microcomputer configuration with first and second CPUs that execute identical control programs in parallel, utilizing a write control unit and determination unit to manage write access, allowing direct connection of one CPU to the determination unit and the system bus, preventing contention and maintaining processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two processor cores access a switch device via dedicated paths, then reliability is improved through lockstep monitoring, but device complexity increases due to dedicated paths and switch device requirements
Solution Approach 1:
The patent merges the paths of two processor cores by allowing them to share a common system bus and access the same memory resources through shared addresses. This eliminates the need for dedicated paths and switch devices while maintaining lockstep monitoring capability through address comparison between the two cores.
Solution Approach 2:
The system enables a single memory resource to serve multiple processor cores simultaneously through universal addressing. The memory can be accessed by either CPU 0 or CPU 1 depending on which core generates the valid write address, making the memory system multi-functional rather than requiring dedicated memory spaces for each core.
2Productivity
If two CPUs access the same address simultaneously, then processing efficiency is maintained, but contention occurs on the system bus leading to reduced productivity
Solution Approach 1:
The system uses feedback through address comparison to manage bus access. The write address from CPU 1 is compared with the read address from CPU 0, and based on this feedback, the system determines whether to allow the write operation. This prevents bus contention by ensuring only one CPU accesses the memory at a time while maintaining processing efficiency through automated arbitration.
3Reliability
If dedicated paths are used for each CPU, then abnormality detection is improved, but manufacturing precision requirements increase due to path matching constraints
Solution Approach 1:
The system creates a copy of the address from one CPU path and compares it with the address from the other CPU path. By copying the write address from CPU 1 and comparing it with the read address from CPU 0, the system maintains lockstep monitoring accuracy without requiring precise physical path matching, thereby reducing manufacturing precision requirements.
Data Source
AI summary
A microcomputer including first and second CPUs is provided. The first and second CPUs may execute identical control programs in parallel. The microcomputer may control a write access by the first or second CPU. The microcomputer may compare an output of the first CPU with an output of the second CPU. Data is written to a write target unit. The microcomputer outputs a write response signal to the first and second CPUs when a data write destination of the first and second CPUs is the write target unit. The microcomputer outputs an abnormality determination signal when data output from the first CPU mismatches with data output from the second CPU. The microcomputer writes the data to the write target unit when the data write destination of the first and second CPUs is the write target unit and the abnormality determination signal is not input.