Lockstep Register Diagnosis Fast Bus Module
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Solution Overview
Problem
Traditional methods for diagnosing lockstep registers in slow clock domains are inefficient due to the slow interface clock, leading to prolonged reading times and reduced system efficiency.
Innovation Solution
A system and method that utilize a central processing unit (CPU) in conjunction with a fast bus module to read and record values from both the functional IP core and lockstep IP core registers, determining normalcy by comparing values and state changes, while employing a delay module to manage clock cycles and avoid metastable states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a same-frequency lockstep interface (APB) is used to read lockstep register values, then the reading process is simple and straightforward, but the reading time becomes excessively long when the interface clock is slow, greatly reducing system efficiency
Solution Approach 1:
The patent segments the register reading process into two independent phases: (1) fast reading of functional IP core registers during fast clock cycles, and (2) slow reading of lockstep IP core registers during slow clock cycles. This segmentation allows each phase to operate at its optimal speed without being constrained by the slow clock domain, thereby resolving the contradiction between reading simplicity and reading speed.
Solution Approach 2:
The patent performs preliminary reading of the functional IP core registers during fast clock cycles before the slow clock domain needs to access them. By pre-reading and storing these values, the system eliminates the need to wait for slow clock cycles to perform readings, thus reducing overall bus time consumption while maintaining reading simplicity.
2Speed
If the interface clock speed is increased to improve reading efficiency, then the reading and determination speed improves, but the system may encounter metastable states and timing issues in slow clock domains
Solution Approach 1:
The patent introduces an intermediary mechanism (the fast bus module coupled with the CPU) that mediates between the fast clock domain and slow clock domain. This intermediary allows fast readings to occur in the fast clock domain while properly synchronizing with the slow clock domain, thus achieving high reading speed without causing metastable states or timing issues.
Solution Approach 2:
The patent implements dynamic clock domain handling by allowing the system to switch between fast clock operations (for reading functional IP core registers) and slow clock operations (for reading lockstep IP core registers and determining normalcy). This dynamic approach allows the system to optimize reading speed when possible while maintaining reliability when synchronization is required.
Data Source
AI summary
A system for diagnosing a register of a lockstep module of a slow clock domain, includes a functional intellectual property (IP) core and a lockstep IP core configured to work in the slow clock domain, a fast bus module configured to read a value of a register of the functional IP core and a value of a register of the lockstep IP core, and record a state change of the register of the functional IP core, and a central processing unit (CPU) configured to determine whether the register of the functional IP core and the register of the lockstep IP core are normal according to the value of the register of the functional IP core, the value of the register of the lockstep IP core, and the state change of the register of the functional IP core.