Lockstep SoC Fault Injection for Transient Error Testing

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Solution Overview

Problem

Existing lockstep architecture testing techniques in system-on-chips (SoCs) are limited by static fault injection, leading to unreliable testing due to uncontrolled functional circuit operation and failure to detect transient faults, particularly during metastable states.

Innovation Solution

A lockstep testing system that injects transient faults using a fault injection circuit, coupled with a checker circuit to accurately detect faults and generate a fault indication signal, ensuring reliable testing without altering functional circuit codes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If static fault injection is used to test lockstep architecture, then testing implementation is simple, but testing reliability is poor and transient faults cannot be detected

Engineering Contradiction:
Improvetesting reliabilityVSAvoidtesting system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by transitioning from static fault injection to dynamic transient fault injection. The testing system introduces time-varying fault conditions that simulate real-world transient errors, making the fault injection process dynamic rather than static. This resolves the contradiction by improving testing reliability through realistic fault simulation while accepting increased system complexity as a necessary trade-off.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements preliminary action by preparing controlled test environments and pre-defining transient fault scenarios before actual testing. The system sets up specific test conditions, including metastable state simulations, in advance to ensure reliable and repeatable testing. This approach improves testing reliability by eliminating the uncontrolled operation problem while managing complexity through structured test preparation.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If fault is injected by altering code associated with functional circuit, then fault injection is achieved, but functional circuits operate in uncontrolled manner

Engineering Contradiction:
Improvetesting reliabilityVSAvoidcircuit operation control
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent introduces an intermediary testing layer that sits between the fault injection mechanism and the functional circuits. This intermediary structure allows controlled fault injection without directly altering functional circuit codes, maintaining operation control while achieving reliable fault detection. The intermediary testing framework translates high-level test specifications into controlled low-level fault injections.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If primary or redundant functional circuit operates in metastable state, then real operating conditions are simulated, but testing reliability degrades

Engineering Contradiction:
Improvemetastable state testing capabilityVSAvoidtesting reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by implementing detection and correction mechanisms that anticipate and counteract the reliability-degrading effects of metastable states. The testing system includes preliminary checks and control measures that identify metastable conditions and prevent them from compromising test results. This approach maintains the ability to test metastable state scenarios while preserving overall testing reliability through proactive mitigation.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentEP4080367B1Testing of lockstep architecture in system-on-chips
Publication Date: 2025.12.31 NXP BV
  • EP4080367B1 patent drawingFigure 1
  • EP4080367B1 patent drawingFigure 2A
  • EP4080367B1 patent drawingFigure 2B

AI summary

A lockstep testing system includes a lockstep controller that generates various control signals. The lockstep testing system further includes various lockstep circuitries, with each lockstep circuitry including primary and redundant functional circuits that are operable in a lockstep mode, and a fault injection circuit that receives a control signal from the lockstep controller and injects a transient fault in the corresponding lockstep circuitry. The transient fault can be injected at one of input and output stages of the primary and redundant functional circuits. Each lockstep circuitry further includes a checker circuit that tests whether the corresponding lockstep circuitry is faulty (i.e., whether the injected fault is accurately detected), and generates and provides, to the lockstep controller, a fault indication signal indicating whether the corresponding lockstep circuitry is faulty.