Lockstep Processor Thread Isolation for Fault Management
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Solution Overview
Problem
Conventional lockstep processing systems in multi-threaded environments face challenges in fault detection and management, leading to unnecessary shutdowns of all threads when a fault is detected in one thread, which conflicts with the goal of maintaining higher functional availability during faults.
Innovation Solution
A method and apparatus that compare internal state signals from lockstep processor cores to detect mismatches, allowing for the identification and reset of only the faulty thread, while keeping other threads operational, utilizing a supervisor component to manage mismatches and differentiate between soft and hard faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lockstep implementations stop all threads upon fault detection, then system reliability is improved through fault detection, but system availability deteriorates due to unnecessary shutdown of non-faulty threads
Solution Approach 1:
The patent segments the fault handling scope from system-wide to thread-specific. Instead of stopping all threads when a fault is detected in one thread, the system identifies and isolates only the faulty thread for resetting. This segmentation allows non-faulty threads to continue executing, thereby maintaining system availability while still ensuring reliability through proper fault detection and containment.
2Productivity
If multi-threaded cores are used to increase performance, then productivity is improved, but fault management complexity increases because a fault in one element causes mismatch across all threads
Solution Approach 1:
The patent applies segmentation by dividing the multi-threaded core into independent thread contexts, each with its own state. When a mismatch is detected, the system can identify which specific thread context is affected and reset only that context. This segmentation reduces fault management complexity compared to treating the entire multi-threaded core as a single unit, allowing selective recovery of non-faulty threads.
Solution Approach 2:
The patent implements local quality by applying different fault handling actions to different threads based on their individual fault status. Non-faulty threads continue running with normal priority, while the faulty thread is reset. This localized approach to fault management reduces overall complexity by avoiding uniform system-wide responses.
3Measurement precision
If internal state signals are compared to detect mismatches, then measurement precision is improved for fault detection, but device complexity increases due to the need for supervisor components and signal comparison mechanisms
Solution Approach 1:
The supervisor component in the patent performs multiple functions: it monitors internal state signals from processor cores, compares these signals to detect mismatches, identifies the specific faulty thread context, and initiates appropriate reset actions. By consolidating these diverse functions into a single supervisor component, the patent reduces overall device complexity compared to having separate dedicated circuits for each function, while maintaining high measurement precision for fault detection.
Data Source
AI summary
A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.