Lockup Latch Timing Structure for Hold Violation Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for delaying data in integrated circuits to prevent hold time violations often increase current leakage and power consumption by requiring additional transistors, which complicates design and control.
Innovation Solution
A structure incorporating a launch pulse latch, a capture pulse latch, and a lockup latch within the data path, where the lockup latch is driven by an inverse clock signal to delay data by a half cycle, reducing the need for additional buffers and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay buffers are used to delay data in the data path, then hold time violations are prevented, but current leakage and power consumption increase significantly
Solution Approach 1:
A lockup latch is introduced as an intermediary element between the launch pulse latch and capture pulse latch. This lockup latch captures data on the opposite clock edge and holds it temporarily, providing the necessary delay to prevent hold time violations without requiring multiple conventional delay buffers, thereby reducing current leakage and power consumption
2Reliability
If conventional delay buffers are used to delay data in the data path, then hold time violations are prevented, but the number of transistors increases substantially
Solution Approach 1:
The lockup latch merges the delay function with the existing pulse latch structure. By utilizing the complementary clock edge already present in the circuit and combining the delay functionality into a single latch element rather than multiple separate buffers, the design reduces the total number of transistors while maintaining hold time compliance
3Reliability
If conventional delay buffers are used to delay data in the data path, then hold time violations are prevented, but design and control complexity increases
Solution Approach 1:
Instead of delaying data using conventional buffers driven by the same clock edge, the lockup latch is driven by the inverse clock edge. This inversion approach naturally provides the required delay window without complex control logic, simplifying both design and control while ensuring hold time compliance
Data Source
AI summary
Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.