Lock-Up Latch Timing for DET Flip-Flop Scan Domain Crossing
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Solution Overview
Problem
Existing data processing circuits face challenges in efficiently propagating scan signals across different clock domains without violating hold time requirements, particularly when using dual-edge-triggered flip-flops (DET) and single-edge-triggered flip-flops (SET) in sequential circuits.
Innovation Solution
Incorporating a lock-up latch that propagates scan signals from one clock domain to another by responding to the opposite phase edge of the clock signal, ensuring that hold time requirements are met for both DET and SET flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dual-edge-triggered flip-flop is used to propagate scan signals across clock domains, then signal propagation speed is improved, but hold time requirements may be violated
Solution Approach 1:
The patent introduces a lock-up latch as an intermediary component between the DET flip-flop and the SET flip-flop. This latch captures the output of the DET flip-flop and holds it stable until the next clock edge, preventing hold time violations while maintaining the speed benefits of DET operation. The latch acts as a buffer that decouples the timing requirements of the two flip-flops.
Solution Approach 2:
The lock-up latch performs preliminary action by capturing and stabilizing the signal from the DET flip-flop before it reaches the SET flip-flop. This preliminary stabilization ensures that the signal is ready and stable when needed, preventing hold time violations without requiring slower DET operation.
2Reliability
If a lock-up latch is added to prevent hold time violations, then reliability is improved, but device complexity increases
Solution Approach 1:
The lock-up latch is applied locally only at critical interfaces between clock domains where hold time violations occur, rather than throughout the entire scan path. This localized application provides the necessary reliability improvement while minimizing the increase in overall device complexity.
Solution Approach 2:
The invention changes the operational parameters of the latch by configuring it to be transparent during specific clock phases and opaque during others, allowing it to integrate seamlessly into the existing scan path without requiring major structural modifications to the surrounding circuitry.
Data Source
AI summary
An apparatus, including: a first flip-flop including a scan input configured to receive a scan signal, a clock input configured to receive a first clock signal of a first clock domain; a latch including an input coupled to an output of the first flip-flop, a clock input configured to receive a control signal; and a second flip-flop including a scan input coupled to an output of the latch, a clock input configured to receive a second clock signal of a second clock domain, and an output configured to generate the scan signal, wherein at least one of the first or second flip-flop comprises a first dual-edge-triggered (DET) flip-flop.