LOCOS Dielectric Fillet Layout for High-Voltage Breakdown Relief
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Solution Overview
Problem
High voltage MOS transistors experience dielectric breakdown at the neck or bird's-beak of the dielectric layer, leading to potential device failure and system inoperability.
Innovation Solution
Incorporating a fillet in the dielectric layer at the intersection of linear sections to reduce the probability of dielectric breakdown by shifting the bird's-beak away from high electric field areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard LOCOS dielectric layer is formed without fillets, then the manufacturing process is simpler, but dielectric breakdown occurs at the neck or bird's-beak regions leading to device failure
Solution Approach 1:
The patent applies curvature by adding fillets at the corners of the thick portion of the dielectric layer. Instead of sharp corners, the fillets create rounded transitions that eliminate the neck or bird's-beak regions where dielectric breakdown previously occurred. This curvature modification redistributes the electric field more evenly, preventing concentration at sharp corners and thereby improving dielectric reliability without significantly complicating the manufacturing process.
2Reliability
If the dielectric layer has uniform thickness, then the structure is simpler, but it cannot provide adequate field relief at high voltage regions
Solution Approach 1:
The patent implements local quality by creating a non-uniform dielectric layer thickness with a thick portion strategically positioned to provide field relief at high voltage regions. The thick portion has lateral dimensions and corner fillets that locally increase dielectric strength where electric field concentration occurs, while other regions maintain standard thickness. This localized thickening with filleted corners provides targeted protection against dielectric breakdown without requiring uniform thickness increase throughout the entire dielectric layer.
Data Source
AI summary
An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter.


