LOCOS Fillet Layout for High-Voltage MOS Breakdown Control

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Solution Overview

Problem

High voltage MOS transistors experience dielectric breakdown at the neck or bird's-beak of the dielectric layer, leading to device failure and system inoperability.

Innovation Solution

Incorporating a fillet in the dielectric layer at the intersection of linear sections, which reduces the probability of dielectric breakdown by shifting the bird's-beak away from high electric field areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional dielectric layer with linear sections is used in high voltage MOS transistors, then the device structure is simple and easy to manufacture, but dielectric breakdown occurs at the neck or bird's-beak region leading to device failure

Engineering Contradiction:

Improvedielectric breakdown resistanceVSAvoiddielectric layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies curvature by replacing the sharp corner intersection of linear dielectric sections with a filleted (curved) transition. This fillet has a specified radius of curvature (e.g., 0.5μm to 2μm) that eliminates the high electric field concentration at sharp corners, thereby preventing dielectric breakdown at the bird's-beak region while maintaining overall structural simplicity

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The patent implements local quality by applying the fillet only at specific critical locations (corner regions where dielectric sections intersect) rather than uniformly across the entire dielectric layer. This localized modification addresses the breakdown problem at high-field regions without unnecessarily complicating the overall device structure

Inventive Principle:

Principle #3Local quality

2Reliability

If the dielectric layer thickness is increased to prevent breakdown, then dielectric strength improves, but the device area increases and integration density decreases

Engineering Contradiction:

Improvedielectric strengthVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent uses different dielectric thicknesses at different locations: a first thickness in contact with the semiconductor layer and a greater second thickness over the semiconductor layer. This localized thickness variation provides enhanced breakdown resistance only where electric fields are strongest, without uniformly increasing the device area

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20260059786A1Locos fillet for drain reduced breakdown in high voltage transistors

Publication Date: 2026.02.26 TEXAS INSTRUMENTS INC

AI summary

An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter. .