LOCOS Gate Oxide for STI High Voltage MOSFETs
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Solution Overview
Problem
High voltage MOSFETs face integration challenges with shallow trench isolation (STI) technology due to gate dielectric etching issues and slower silicon oxide growth rates at STI edges, leading to degraded gate oxide integrity.
Innovation Solution
Implementing a LOCOS dielectric as the gate oxide, spaced apart from STI within an STI ring, allowing the transistor gate electrode to sit on top of the LOCOS gate oxide for consistent thickness and avoiding conventional gate dielectric etching problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If STI is used for device isolation, then IC density requirements are met with zero oxide field encroachment, but gate oxide integrity is degraded due to gate dielectric thinning at STI edges
Solution Approach 1:
A LOCOS dielectric layer is introduced as an intermediary between the gate electrode and the STI structure. This LOCOS dielectric is spaced apart from the STI by a first distance, preventing direct interaction between the gate dielectric and STI edges that causes thinning. The LOCOS dielectric acts as a buffer that maintains consistent gate oxide thickness while allowing STI to provide effective device isolation.
2Ease of manufacture
If conventional MOS gate structures are used with STI, then integration into STI-based technologies is attempted, but gate dielectric etching problems arise that degrade transistor performance
Solution Approach 1:
The LOCOS dielectric serves as a protective intermediary that prevents gate dielectric etching issues. By spacing the LOCOS dielectric apart from the STI structure, the patent eliminates the need for aggressive gate dielectric etching that would otherwise be required to remove non-needed gate and dummy dielectrics near STI edges, thereby maintaining precise gate dielectric thickness control.
Solution Approach 2:
The LOCOS dielectric is formed in advance as part of the gate structure fabrication process. This preliminary formation of the LOCOS dielectric layer, spaced from STI, prevents subsequent gate dielectric etching problems before they can occur during later processing steps.
3Ease of manufacture
If gate dielectric etching is performed to remove non-needed dielectrics, then excess oxide is removed, but gate oxide integrity is compromised at STI edges
Solution Approach 1:
The LOCOS dielectric acts as a sacrificial intermediary that can be selectively removed without compromising the main gate oxide. The spacing between the LOCOS dielectric and STI ensures that when gate dielectric etching is performed to remove non-needed gate and dummy dielectrics, the main gate oxide integrity at STI edges is protected from thinning or damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement prevents gate dielectric thinning at STI edges, maintaining consistent gate oxide integrity and enabling seamless integration of high voltage MOSFETs into STI-based technologies without the gate oxide integrity issue.
Implementation Method 1
the entire LOCOS structure is thermally grown
Data Source
AI summary
An electronic device includes an isolated region surrounded by an isolation ring over a semiconductor substrate. A well of a first conductivity type is located within the isolated region. A source region and a drain region of a second conductivity type are located over the well. A local-oxidation-of-silicon (LOCOS) layer is located on the well between the source and the drain, between the source and the isolation ring, and between the drain and the isolation ring. A gate electrode located between the source and the drain on said LOCOS layer.